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检索条件"任意字段=IEE Colloquium on Field Programmable Gate Arrays - Technology and Applications"

共 52 条记录，以下是1-10 订阅

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Implementation Research of Tiny ML on RISC-V Platform Using Efinix Platform for Real Time Person Detection

Implementation Research of Tiny ML on RISC-V Platform Using ...

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International colloquium on Signal Processing & Its applications, CSPA

作者： Yeap Wei Hao Cheong Choon Min Roslee Mohd Sabri Richard Lai Tian Fat Su Hsiao Wei Hazwan Halim Solahuddin Yusuf Fadhlullah School of Engineering INTI international College Penang Bayan Lepas Pulau Penang Malaysia MIMOS Berhad Technology Park Malaysia Bukit Jalil Kuala Lumpur Malaysia

ISBN: (数字)9798331522193

ISBN: (纸本)9798331522209

The rapid advancements in artificial intelligence (AI) and computer vision have revolutionized intelligent security systems, addressing challenges related to cost, efficiency, and scalability. This paper investigates the application of Tiny Machine Learning (TinyML) on the RISC-V platform, utilizing the Efinix Ti60 F225 FPGA for real-time person detection. The study aims to harness the energy efficiency, flexibility, and scalability of the RISC-V architecture to develop a cost-effective and sustainable solution for intelligent security applications. The proposed system combines the YOLO model for person detection with TinyML techniques, enabling real-time processing while maintaining an accuracy of 80% for individuals within a 2-meter range. Hardware components, such as the Raspberry Pi Camera Module V2 and Mini DSI Panel, were employed to capture and display real-time imagery. Comprehensive evaluations demonstrated the system's performance advantages, including reduced latency, low power consumption, and minimal bandwidth usage, emphasizing the benefits of deploying AI at the edge. Although challenges such as environmental variability and memory limitations were encountered, the findings highlighted the potential of integrating TinyML with RISC-V platforms for intelligent security applications. The results contributed to the field of edge computing and open-source hardware, presenting a viable approach to energy-efficient and scalable AI solutions. Future research will focus on overcoming hardware constraints, extending the detection range, and incorporating adaptive learning capabilities to enhance system robustness and functionality further.

关键词： YOLO Reduced instruction set computing Costs Tiny machine learning Scalability Real-time systems Energy efficiency Security Artificial intelligence field programmable gate arrays

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Automatic Test Case Generation for Prime field Elliptic Curve Cryptographic Circuits

Automatic Test Case Generation for Prime Field Elliptic Curv...

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International colloquium on Signal Processing & Its applications, CSPA

作者： Krishn Kumar Gupt Meghana Kshirsagar Joseph P. Sullivan Conor Ryan Limerick Institute of Technology Limerick Ireland University of Limerick Limerick Ireland

ISBN: (数字)9781665414845

ISBN: (纸本)9781665430593

Elliptic curve is a major area of research due to its application in elliptic curve cryptography. Due to their small key sizes, they offer the twofold advantage of reduced storage and transmission requirements. This also results in faster execution times. The authors propose an architecture to automatically generate test cases, for verification of elliptic curve operational circuits, based on user-defined prime field and the parameters used in the circuit to be tested. The ECC test case generations are based on the Galois field arithmetic operations which were the subject of previous work by the authors. One of the strengths of elliptic curve mathematics is its simplicity, which involves just three points (P, Q, and R), which pass through a line on the curve. The test cases generate points for a user-defined prime field which sequentially selects the input vector points (P and/or Q), to calculate the resultant output vector (R) easily. The testbench proposed here targets field programmable gate array (FPGAs) platforms and experimental results for ECC test case generation on different prime fields are presented, while ModelSim is used to validate the correctness of the ECC operations.

关键词： VHDL Elliptic curves Elliptic curve cryptography Generators Cryptography Integrated circuit modeling field programmable gate arrays

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Principal Component Analysis Approach in Selecting Type-1 and Type-2 Fuzzy Membership Functions for High-dimensional Data 17

Principal Component Analysis Approach in Selecting Type-1 an...

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Joint 17th World Congress of International-Fuzzy-Systems-Association / 9th International Conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Raj, Desh Gupta, Aditya Tanna, Kenil Garg, Bhuvnesh Rhee, Frank Chung-Hoon Indian Inst Technol Guwahati Dept Comp Sci & Engn Gauhati 781039 India Indian Inst Technol Guwahati Dept Math Gauhati 781039 India Hanyang Univ Dept Elect & Commun Engn Ansan 15588 South Korea

ISBN: (纸本)9781509049172

With increased interest in learning from data, algorithms that manipulate datasets containing hundreds of features have become popular in various fields such as medicine, image processing, geolocation, biochemistry, and computational linguistics. Since a number of these applications exploit the power of fuzzy sets in representing uncertainties, it may be considered essential to describe a method for selecting the most suitable fuzzy membership function to represent a high-dimensional dataset. In this paper, we propose such a method, which is based on dimensionality reduction using the Principal Component Analysis (PCA) technique, followed by the Wilcoxon Minimal Bin Size algorithm, which has earlier been evaluated on multidimensional datasets up to 8 dimensions. We further demonstrate our proposed method using two real datasets consisting of 281 and 500 features, respectively.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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A codec technology research to counter laser high PRF jamming based on FPGA 7

A codec technology research to counter laser high PRF jammin...

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2016 7th ieeE Control and System Graduate Research colloquium, ICSGRC 2016

作者： Qingzhong, Jia Xingdou, Wang Key Ministry Education Laboratory of Dynamics and Control of Flight Vehicle Beijing Institute of Technology BIT Beijing China

ISBN: (纸本)9781509011759

Through analysis of coding and decoding principle about countering the laser jamming, this paper focuses on a long and cyclic period of pseudo-random codec scheme, and it uses FPGA to implement the program according to the specific hardware requirements in order to achieve a better effect. The design is mainly used to counter the laser high PRF (pulse repetition frequency) jamming, of which implementation process includes specifically generating a uniformly distributed pseudorandom pulse and the coding and decoding section. This paper not only demonstrates the detailed derivation of scheme and each part of specific implementation process, also analyzes the impact of codec by elements in the scheme, such as the frequency of pseudo-random pulse, the number of short period pulses and short period. Finally, the close combining hardware and software of implementation processes illustrate adequately the advantages in the simple principle of scheme, the convenient binding parameter, and the obvious anti-interference effect, that will be remarkable for the engineering applications. © 2016 ieeE.

关键词： field programmable gate arrays (FPGA)

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CORDIC-based FFT real-time processing design and FPGA implementation

CORDIC-based FFT real-time processing design and FPGA implem...

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International colloquium on Signal Processing & Its applications, CSPA

作者： Aimei Tang Li Yu Fangjian Han Zhiqiang Zhang School of Electronic Science and Engineering National University of Defense Technology Changsha China

ISBN: (纸本)9781467387811

This paper presents a designing scheme of high-speed real-time serial pipelined Fast Fourier Transform (FFT) processor on FPGA which is based on Coordinate Rotation Digital Computer (CORDIC) algorithm. The CORDIC algorithm will reduce the hardware complexity compared to the direct implementation of the butterflies using complex multipliers. Moreover, the design uses the butterflies of the radix-2 Decimation-In-Time (DIT) algorithm, the dual-port RAM and the pipelined structure, which will sufficiently increase the performances of the FFT processor. The simulation results show that compared with the same type of real-time FFT processor, the scheme presented in this paper reduces the hardware resource requirements of Adaptive Look-up Tables (ALUTs) and increase the Signal Noise Ratio (SNR) by about 25dB.

关键词： Random access memory Signal processing algorithms Algorithm design and analysis Real-time systems field programmable gate arrays MATLAB Hardware

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VHDL simulation of peak detector, 64 bit BCD counter and reset automatic block for PD detection system using FPGA

VHDL simulation of peak detector, 64 bit BCD counter and res...

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International colloquium on Signal Processing & Its applications, CSPA

作者： Emilliano Chandan Kumar Chakrabarty Ahmad Basri A. Ghani Agileswari K. Ramasamy Department of Electronics and Communication Engineering College of Engineering Universiti Tenaga Malaysia (UNITEN) Selangor Darul Ehsan Malaysia

ISBN: (纸本)9781424471218

Currently, FPGA (field programmable gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 9.2i (Xilinx) and Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of field Programming gate Array (FPGA) for the detection and counting of partial discharge signals in underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The impulse signals will be processed, detected and counted using ADC with peak detector block, counter with reset block and reset automatic block.

关键词： Counting circuits field programmable gate arrays Partial discharges Radiation detectors Signal processing Acoustic signal detection Signal synthesis Signal detection Probes Latches

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An FPGA-based implementation of variable fractional delay filter

An FPGA-based implementation of variable fractional delay fi...

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International colloquium on Signal Processing & Its applications, CSPA

作者： Ussanai Nithirochananont Sorawat Chivapreecha Kobchai Dejhan Department of Telecommunications Engineering Faculty of Engineering King Mongkut''s Institute of Technology Ladkrabang Bangkok Thailand

A variable fractional delay (VFD) filter is widely used in applications such as symbol timing recovery, arbitrary sampling rate conversion and echo cancellation. This paper presents an implementation of variable fractional delay filter on FPGA. The implementation utilizes an efficient structure so called Taylor structure. The main advantage of this structure is to reduce number of multiplier and adder when compared with Farrow structure or modified Farrow structure. The result of implementation will be reported as throughput and area utilization.

关键词： Finite impulse response filter field programmable gate arrays Delay effects Lagrangian functions Interpolation Arithmetic Transfer functions Timing Echo cancellers Throughput

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Exploiting real-time FPGA based adaptive systems technology for real-time sensor fusion in next generation automotive safety systems

Exploiting real-time FPGA based adaptive systems technology ...

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iee Seminar on Target Tracking: Algorithms and applications

作者： Chappell, Steve Macarthur, Alistair Preston, Dan Olmstead, Dave Flint, Bob Sullivan, Chris Celoxica Ltd 66 Milton Park Abingdon Oxfordshire OX14 4RX United Kingdom Medius Inc. 911 Western Ave Seattle WA 98104 United States BAE SYSTEMS Ventures Warwick House Aerospace Centre Farnborough GU14 6YU United Kingdom

ISBN: (纸本)086341608X

We present a system for the boresighting of sensors using inertial measurement devices as the basis for developing a range of dynamic real-time sensor fusion applications. The proof of concept utilizes a COTS FPGA platform for sensor fusion and real-time correction of a misaligned video sensor. We exploit a custom-designed 32-bit soft processor core and C-based design & synthesis for rapid, platform-neutral development. Kalman filter and sensor fusion techniques established in advanced aviation systems are applied to automotive vehicles with results exceeding typical industry requirements for sensor alignment. Results of the static and the dynamic tests demonstrate that using inexpensive accelerometers mounted on (or during assembly of) a sensor and an Inertial Measurement Unit (IMU) fixed to a vehicle can be used to compute the misalignment of the sensor to the IMU and thus vehicle. In some cases the model predications and test results exceeded the requirements by an order of magnitude with a 3-sigma or 99% confidence. © Celoxica Ltd.

关键词： field programmable gate arrays (FPGA)

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Analysis of FPGA-based AES round architectures

Analysis of FPGA-based AES round architectures

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iee Irish Signals and Systems Conference

作者： Bermingham, David Wang, Xiaojun Bin, Liu School of Electronic Engineering Dublin City University Dublin Ireland Department of Computer Science and Technology Tsinghua University Beijing China

This paper explores the power, delay and area efficiency of AES round architectures when implemented on field-programmable gate arrays (FPGAs). Modern FPGAs provide attractive solutions for cryptographic applications when compared to Application Specific Integrated Circuits (ASIC) design, reducing costs, allowing greater flexibility and can provide high throughput. There has been a varied number of AES architectures proposed since 2001 for implementation on FPGAs. In this paper we implement three popular AES round architectures, allowing for analysis and comparison of the area/delay/power tradeoffs when mapped to Xilinx VirtexII-Pro FPGAs.

关键词： field programmable gate arrays

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Dynamic noise texture generation on FPGAs

Dynamic noise texture generation on FPGAs

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International Conference on Communications, Circuits and Systems

作者： Li, XY Wu, EH Univ Macau Fac Sci & Technol Macau Peoples R China

ISBN: (纸本)0780390156

FPGA technology provides a fast prototyping way to implement various algorithms on its reconfigurable hardware platform. It can flexibly handle with different applications. In this paper, procedural texture mapping based on Perlin noise function is implemented on a Xilinx FPGA prototyping board. Hardware design can deal with this intensive per-pixel computation much better. Realistically and interestingly natural-appearing material effects like wood, marble and fire can be generated and dynamically varying. A new Perlin noise function is adopted which is targeted to circuit structure with low cost of hardware resources. Arithmetic units such as addition and multiplication modules are highly reused in the circuit design.

关键词： field programmable gate arrays

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