Concurrent Logic CLi6000 devices are high granularity, RAM-based reconfigurable FPGAs. The architecture consists of a grid of small cells surrounded by programmable input/output blocks and programmable interconnect. T...
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Concurrent Logic CLi6000 devices are high granularity, RAM-based reconfigurable FPGAs. The architecture consists of a grid of small cells surrounded by programmable input/output blocks and programmable interconnect. This paper proposes a logic synthesis procedure for complex designs. A register transfer level description of the design can be optimized using multi-level synthesis techniques and then mapped to the FPGA.< >
Investigates adaptive error correction for magnetic recording systems using a computer-controlled fieldprogrammablegate array device (FPGA). The gate array has been employed in a prototype, variable depth, error-cod...
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Investigates adaptive error correction for magnetic recording systems using a computer-controlled fieldprogrammablegate array device (FPGA). The gate array has been employed in a prototype, variable depth, error-code data interleaver. An outline of the application is given followed by performance comparisons with a software-only implementation.< >
FLEX programmable logic offers the major benefits of both FPGAs and EPLDs for the first time in a single device family. The high-register counts, low standby power and in-circuit reconfigurability of FPGAs are combine...
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FLEX programmable logic offers the major benefits of both FPGAs and EPLDs for the first time in a single device family. The high-register counts, low standby power and in-circuit reconfigurability of FPGAs are combined with the high-performance, predictable interconnect delays and ease-of-use of EPLDs make FLEX the ideal solution for high density designs. Designs targeted for FLEX devices can be implemented and modified quickly, providing fast time-to-market and eliminating the burden of high non-reoccurring engineering (NRE) costs associated with gate-array designs. The FLEX8000 family of CMOS devices have interconnect delays which are an order of magnitude smaller than FPGAs making it faster across a wide range of system applications.< >
Illustrates the design flow for a new generation of the dynamically programmable logic device (DPLD), but is also relevant to other technologies. The marketing and commercial phase involves evaluating and patent filin...
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Illustrates the design flow for a new generation of the dynamically programmable logic device (DPLD), but is also relevant to other technologies. The marketing and commercial phase involves evaluating and patent filing of features to be incorporated into a new generation of DPLD. This is presented to potential licensees and with further discussion results in an agreed target specification. The majority of the target specification for a new generation of DPLD is derived from experience of previous DPLD architectures and the licensee market and process requirements. Architectural and CAD features that have been previously analysed to achieve a required performance are re-used extensively. An example of this is the fine-grain DPLD core architecture which is now approaching its 4th generation.< >
In the instrumentation market, as in most high-tech markets, increased competition and time-to-market pressures are making system developers pursue two often conflicting goals: make the system as flexible as possible;...
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In the instrumentation market, as in most high-tech markets, increased competition and time-to-market pressures are making system developers pursue two often conflicting goals: make the system as flexible as possible; and bring it to market as quickly as possible. Adaptive hardware-that is, standard circuitry that can conform to different application requirements-can help system designers successfully meet these two goals, but until now adaptive hardware has been limited and costly in the instrumentation market. A new enabling technology has been patented-Cache Logic-that makes it possible to use adaptive hardware in a variety of instrumentation applications. This paper looks at how Cache Logic might be used in a data acquisition product.< >
SRAM based FPGAs are commonly used for rapid prototyping and hardware emulation, as well as for the 'mopping up' of 'glue logic' and the customisation of mass produced hardware. A less common applicati...
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SRAM based FPGAs are commonly used for rapid prototyping and hardware emulation, as well as for the 'mopping up' of 'glue logic' and the customisation of mass produced hardware. A less common application of FPGAs is in the area of computation. This is, perhaps, because the limited capacity of the FPGAs, unless used in very large numbers (as in the case of some commercially available hardware emulators), seems to exclude the implementation of the complex hardware units (floating point units, etc.) often associated with computation. However, the situation is not this bleak because there is a large class of so called generalised cellular automata problems that can be profitably tackled using custom hardware constructed using FPGAs.< >
Expressions that relate the unwanted sidebands level to the frequency increment and its update rate of a digitally generated chirp signal were presented. These show that high frequencies can be generated with a synthe...
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Expressions that relate the unwanted sidebands level to the frequency increment and its update rate of a digitally generated chirp signal were presented. These show that high frequencies can be generated with a synthesizer that employs high speed logic and a low speed frequency accumulator which can be implemented in a gate array. A prototype 2.5 MHz frequency generator was realized in two gatearrays which incorporated the double accumulator and logic to control the sweep parameters.
作者：
Ma, XJTong, JRFudan Univ
Microelect Dept ASIC & Syst State Key Lab Shanghai 200433 Peoples R China
FPGA is widely applied in datapath applications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDE...
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ISBN:
(纸本)078037889X
FPGA is widely applied in datapath applications, so it's all important design issue to contrive FPGA architecture fit for datapath circuit implementation. In this paper, we described a new FPGA architecture -- FDEGA (field-programmable Datapath Enhanced gate Array). The LC of FDEGA is optimized for datapath implementation. and can be programmed as either combinational or sequential device. FDEGA has hierarchical interconnection architecture. A chip with 16*16 LC array has been fabricated, and the design of LC and interconnection has been tested, and circuit sample chosen from practical digital system design has been implemented in FDEGA. The result proves that our design of FDEGA is correct.
In this paper, the techniques developed to implement an auto-generator for the transfer of a design, developed using the FPGA based XILINX platform, to the VLSI based MAGIC platform is described. This allows a gate le...
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In this paper, the techniques developed to implement an auto-generator for the transfer of a design, developed using the FPGA based XILINX platform, to the VLSI based MAGIC platform is described. This allows a gate level design to be conveniently translated into a transistor level design. The provisions made available on the FPGA-Xilinx to support the development of designs using logic gates and to perform functional simulations, without having to resort to the Configurable Logic Block (CLB) based implementations on the fieldprogrammablegatearrays (FPGAs), has been incorporated to facilitate this automatic translation process. This systematic translation of a FPGA-Xilinx netlist file to the corresponding VLSI-Magic netlist file has been described with the help of a suitable example. Extensive evaluations of this translation process confirm that the proposed approach is highly, desirable, as it eliminates the need for detailed familiarization of the VLSI based MAGIC design platform.
This paper presents a track assignment algorithm for the hierarchical fieldprogrammablegatearrays (HFPGA). Given a netlist and a hierarchical FPGA, the hierarchical FPGA is first collapsed into a single-level HFPGA...
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This paper presents a track assignment algorithm for the hierarchical fieldprogrammablegatearrays (HFPGA). Given a netlist and a hierarchical FPGA, the hierarchical FPGA is first collapsed into a single-level HFPGA to find the initial routing results. Two kind of routing structures, disjoint and overlapped structure, are used to specify different routing requirements and improve the routing efficiency. The initial routing for a single-level HFPGA can be transformed to the graph coloring and Stenier tree problems on a graph to route the nets in the disjoint and the overlapped structure, respectively. Finally, the initial routing results are extended to a multi-level HFPGA. Experimental results on a set of MCNC benchmark circuits show that our algorithm is very efficient. Also the 100% routability can be achieved. These results not only validate our claim on the perform of the algorithm but also facilitate the usage of the hierarchical FPGA.
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