The new XC3100 family of static RAM based FPGAs from Xilinx provides the same advantages in terms of initial cost, time to market, reprogrammability and low risk design as Xilinx existing XC2000, XC3000 and XC4000/400...
详细信息
The new XC3100 family of static RAM based FPGAs from Xilinx provides the same advantages in terms of initial cost, time to market, reprogrammability and low risk design as Xilinx existing XC2000, XC3000 and XC4000/4000A/4000H families of FPGAs. However the parts have been optimised at a silicon level for high performance, and open the way to designs running with a system clock of up to 80 MHz, and even beyond. The new devices retain the architecture of the familiar XC3000 family, thus allowing designers to take advantage of their existing designs and design expertise. Pin-out and bitstream compatibility with the existing devices ensure that the transition to the new family, where it is required, will be as painless as possible. In addition a completely new family member, the XC3195 is now available. This device contains a nominal 13500 gates, thus allowing typical utilisations of around 7000 to 9000 gates. This compares with the nominal 9000 and usable 5000 to 7500 gates of the largest XC3000 family member, the XC3090.< >
Illustrates the use of Occam and Ruby in developing a shaft encoder interface. In the joint of a robot arm, a shaft encoder measures the angle of each shaft by reading two output signals generated from photo-sensitive...
详细信息
Illustrates the use of Occam and Ruby in developing a shaft encoder interface. In the joint of a robot arm, a shaft encoder measures the angle of each shaft by reading two output signals generated from photo-sensitive detectors. The light input to these detectors is interrupted by a fine pattern of transparent and opaque regions on a glass disc. Rotating the encoder disc results in two digital pulse streams, and the shaft encoder interface must deduce from these streams the direction of rotation and position. While special-purpose devices such as the Texas Instrument THCT2000 can be used in the interface, the resulting system has a low bandwidth and a high chip-count. The task is to develop a new interface, based on FPGAs, with a higher speed of operation, higher accuracy, additional functionality, smaller physical size, lower development cost, reduced development time, and with increased flexibility.< >
The delay is an important factor in the digital circuit design by FPGA (fieldprogrammablegate Array). According to our knowledge, however, there is few performance oriented technology mapping systems for multiplexor...
详细信息
The delay is an important factor in the digital circuit design by FPGA (fieldprogrammablegate Array). According to our knowledge, however, there is few performance oriented technology mapping systems for multiplexor based FPGAs. In this paper, we present an algorithm with polynomial tune complexity which carries out the performance optimal technology mapping targeting MUX-based FPGAs. The proposed approach is based on the formalization by cluster concept. Our algorithm guarantees optimal mapping results in the level of circuits under the given input circuit structure. The experimental results show that our method is better than mis-pga(new) and TOS in terms of area as well as delay cost.
As part of the design of a knowledge-base server, there arose a requirement for a hardware sub-unit which could perform a general hashing function on variable length tuples. The knowledge-base server uses transputers ...
详细信息
As part of the design of a knowledge-base server, there arose a requirement for a hardware sub-unit which could perform a general hashing function on variable length tuples. The knowledge-base server uses transputers for its internal control. The hardware hasher unit replaces an OCCAM procedure which took an unacceptably long time to execute (about 10 microseconds). The target time was under 160 nanoseconds. The first implementation of the hardware hasher was carried out using conventional GAL technology. This worked at acceptable speed (order of 40 nanoseconds) but the nine GAL chips took up a relatively large amount of PCB area. Hasher designs have since been implemented in Xilinx 3000 series FPGA technology, Altera MAX series 5000 technology, Actel ACT1 technology, National MAPL technology, AMD MACH technology, and Lattice Semiconductor pLSI technology. This paper compares the speed, cost and PCB area for all seven designs. The authors also comment generally on the suitability of each candidate technology for this type of task, and then draw some conclusions which may help to guide future designs in other applications areas.< >
Artificial neural networks have shown good capabilities in medical diagnostic applications. They offer the advantage that they are able to learn the representation by examples, which is of great benefit when the natur...
详细信息
Artificial neural networks have shown good capabilities in medical diagnostic applications. They offer the advantage that they are able to learn the representation by examples, which is of great benefit when the nature of the process is unknown or is difficult to characterise. On the other hand, the hardware implementation of the parallel network structure can dramatically improve the network efficiency. Here, a hardware implementation of neural network based ballistocardiogram (BCG) classification system with fieldprogrammablegatearrays (FPGAs) technology is presented. The specific trained neural network is implemented in Xilinx XC4000 series FPGAs.< >
Plessey Semiconductors Ltd. have recently introduced a novel type of programmable Logic Device categorised as fieldprogrammablegatearrays (FPGAs). Offering exciting opportunities for FPGA applications, the devices ...
详细信息
Plessey Semiconductors Ltd. have recently introduced a novel type of programmable Logic Device categorised as fieldprogrammablegatearrays (FPGAs). Offering exciting opportunities for FPGA applications, the devices are known as Electrically Reconfigurable arrays-ERAs. ERAs allow the user to design and programme devices in their own premises resulting in short design and production lead times with no NRE charges. These features make the devices viable for small production runs and the natural choice of technology where frequent production variations are required to meet specific customer needs.< >
Reconfigurable systems-which modify their operation to adapt to prevailing conditions-promise new and exciting design concepts for the 1990s. Adaption, to date, has primarily been the domain of software, but new hardw...
详细信息
Reconfigurable systems-which modify their operation to adapt to prevailing conditions-promise new and exciting design concepts for the 1990s. Adaption, to date, has primarily been the domain of software, but new hardware techniques of logic design using RAM based silicon open up significant benefits. The author discusses how the Electrically Reconfigurable arrays (ERAs) can be used in adaptive hardware systems. The generic name of SRAM based products such as the ERA is fieldprogrammablegatearrays (FPGAs). Key features to look for in FPGAs for adaptive hardware applications are speed and flexibility of reconfiguration.< >
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors that can download new software over the n...
详细信息
ISBN:
(纸本)0769514715;0769514723
Future networked appliances should be able to download new services or upgrades from the network and execute them locally. This flexibility is typically achieved by processors that can download new software over the network, using JAVA technology. This paper demonstrates that FPGAs are a realistic implementation platform for thin server or client applications. FPGAs can offer the same end-user experience as software based systems, combined with more computational power and lower cost.
Reconfigurable fieldprogrammablegatearrays (FPGAs) are a new technology suitable for building fast and flexible processing systems. This paper contains an overview of the first ever FPGA-based coprocessor for an im...
详细信息
Reconfigurable fieldprogrammablegatearrays (FPGAs) are a new technology suitable for building fast and flexible processing systems. This paper contains an overview of the first ever FPGA-based coprocessor for an image processing system. The system provides the performance of custom hardware with the added flexibility of an equivalent software-based system. Benchmark results are given for the time taken to perform two typical image processing functions.< >
This contribution describes a fieldprogrammablegate Array (FPGA) implementation of exponentiatan over GF (13). of which arithmetic architectures is based on Fermat Number Transform (FNT). The main applications of th...
详细信息
ISBN:
(纸本)078038511X
This contribution describes a fieldprogrammablegate Array (FPGA) implementation of exponentiatan over GF (13). of which arithmetic architectures is based on Fermat Number Transform (FNT). The main applications of the processor are digital signature and authentication schemes. It is then shown how, by decomposing high degree polynomial into several lower degree polynomials to execute multiplication, the area is minimized while the throughput is maximized. The processor consists of special operational blocks for FNT, IFNT, point multiplier, and modular operation. Xc2v1000-4fg256 (Xilinx Virtex2 series FPGA, 100 million gates.) is used to accomplish the computation, and the FPGA implementation result is provided and evaluated. It is shown that it takes 65 its to accomplish once computation.
暂无评论