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检索条件"任意字段=IEE Colloquium on Field Programmable Gate Arrays - Technology and Applications"

共 52 条记录，以下是41-50 订阅

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Design flow for the development of new FPGA architectures

Design flow for the development of new FPGA architectures

引用

iee colloquium on field programmable gate arrays - technology and applications

作者： S.C. Beavis Pilkington Micro-Electronics Limited Cheshire UK

Illustrates the design flow for a new generation of the dynamically programmable logic device (DPLD), but is also relevant to other technologies. The marketing and commercial phase involves evaluating and patent filing of features to be incorporated into a new generation of DPLD. This is presented to potential licensees and with further discussion results in an agreed target specification. The majority of the target specification for a new generation of DPLD is derived from experience of previous DPLD architectures and the licensee market and process requirements. Architectural and CAD features that have been previously analysed to achieve a required performance are re-used extensively. An example of this is the fine-grain DPLD core architecture which is now approaching its 4th generation.< >

关键词： Design automation Logic arrays

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Using FPGAs to implement reconfigurable DSP architectures?

Using FPGAs to implement reconfigurable DSP architectures?

引用

iee colloquium on field programmable gate arrays - technology and applications

作者： S. Monaghan C. Cowen P.D. Noakes Department of Electronic Systems Engineering University of Essex UK

SRAM based FPGAs are commonly used for rapid prototyping and hardware emulation, as well as for the 'mopping up' of 'glue logic' and the customisation of mass produced hardware. A less common application of FPGAs is in the area of computation. This is, perhaps, because the limited capacity of the FPGAs, unless used in very large numbers (as in the case of some commercially available hardware emulators), seems to exclude the implementation of the complex hardware units (floating point units, etc.) often associated with computation. However, the situation is not this bleak because there is a large class of so called generalised cellular automata problems that can be profitably tackled using custom hardware constructed using FPGAs.< >

关键词： Cellular automata Digital signal processors Logic arrays Parallel architectures

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Reconfigurable FPGAs in 80 MHz systems

Reconfigurable FPGAs in 80 MHz systems

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iee colloquium on field programmable gate arrays - technology and applications

作者： N. Sawyer

The new XC3100 family of static RAM based FPGAs from Xilinx provides the same advantages in terms of initial cost, time to market, reprogrammability and low risk design as Xilinx existing XC2000, XC3000 and XC4000/4000A/4000H families of FPGAs. However the parts have been optimised at a silicon level for high performance, and open the way to designs running with a system clock of up to 80 MHz, and even beyond. The new devices retain the architecture of the familiar XC3000 family, thus allowing designers to take advantage of their existing designs and design expertise. Pin-out and bitstream compatibility with the existing devices ensure that the transition to the new family, where it is required, will be as painless as possible. In addition a completely new family member, the XC3195 is now available. This device contains a nominal 13500 gates, thus allowing typical utilisations of around 7000 to 9000 gates. This compares with the nominal 9000 and usable 5000 to 7500 gates of the largest XC3000 family member, the XC3090.< >

关键词： Logic arrays

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Hardware compilation for FPGAs: imperative and declarative approaches for a robotics interface

Hardware compilation for FPGAs: imperative and declarative a...

引用

iee colloquium on field programmable gate arrays - technology and applications

作者： I. Page W. Luk H. Lau Comput. Lab. Oxford Univ. UK Rogramming Research Group Oxford University Computing Laboratory Oxford UK Roboltics Research Group Department of Engineering Science Oxford University Oxford UK

Illustrates the use of Occam and Ruby in developing a shaft encoder interface. In the joint of a robot arm, a shaft encoder measures the angle of each shaft by reading two output signals generated from photo-sensitive detectors. The light input to these detectors is interrupted by a fine pattern of transparent and opaque regions on a glass disc. Rotating the encoder disc results in two digital pulse streams, and the shaft encoder interface must deduce from these streams the direction of rotation and position. While special-purpose devices such as the Texas Instrument THCT2000 can be used in the interface, the resulting system has a low bandwidth and a high chip-count. The task is to develop a new interface, based on FPGAs, with a higher speed of operation, higher accuracy, additional functionality, smaller physical size, lower development cost, reduced development time, and with increased flexibility.< >

关键词： Logic arrays Design automation Manipulators Parallel languages

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Comparing several implementations of a hardware hasher unit

Comparing several implementations of a hardware hasher unit

引用

iee colloquium on field programmable gate arrays - technology and applications

作者： M.J. Lear E. James S.H. Lavington B. Srisuchinwong T.A. York A.M. Somerville Department of Computer Science University of Essex Colchester UK Department of Electrical Eng. & Electronics University of Manchester Institute of Science and Technology Manchester UK

As part of the design of a knowledge-base server, there arose a requirement for a hardware sub-unit which could perform a general hashing function on variable length tuples. The knowledge-base server uses transputers for its internal control. The hardware hasher unit replaces an OCCAM procedure which took an unacceptably long time to execute (about 10 microseconds). The target time was under 160 nanoseconds. The first implementation of the hardware hasher was carried out using conventional GAL technology. This worked at acceptable speed (order of 40 nanoseconds) but the nine GAL chips took up a relatively large amount of PCB area. Hasher designs have since been implemented in Xilinx 3000 series FPGA technology, Altera MAX series 5000 technology, Actel ACT1 technology, National MAPL technology, AMD MACH technology, and Lattice Semiconductor pLSI technology. This paper compares the speed, cost and PCB area for all seven designs. The authors also comment generally on the suitability of each candidate technology for this type of task, and then draw some conclusions which may help to guide future designs in other applications areas.< >

关键词： File systems File servers Knowledge based systems Logic arrays

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Hardware architectures for lattice decoders

Hardware architectures for lattice decoders

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iee colloquium on DSP applications in Communication Systems

作者： A.G. Burr J.A. Sheppard Communications Research Group University of York UK

Describes the implementation of decoders for a combined coding and modulation scheme, lattice coding, using a direct hardware structure. The trellis representation of lattice codes is described, and a hardware decoder structure is developed which maps directly to the trellis. An implementation of this structure for the E8 lattice is described, using field programmable gate arrays (FPGAs). This achieves a coding gain of about 2 dB, and is capable of operation at over 60 Mbit/s. The integration of various software tools, including Workview and SPW, in the design process is also described.< >

关键词： Decoding Encoding Logic arrays Design automation Modulation

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Reconfigurable DSP systems

Reconfigurable DSP systems

引用

iee colloquium on applications Specific Integrated Circuits for Digital Signal Processing

作者： M.A. Wahab D.J. Puckey Department of Electronics and Information Technology University of Glamorgan Mid-Glamorgan UK Dept. of Electron. & Inf. Technol. Glamorgan Univ. Pontypridd UK

Presents a new approach to the implementation of DSP structures that combines many of the benefits of ASIC-based systems with those of DSP processors. It is part of the work that the authors are engaged in to design and implement efficient DSP structures using hard-wired logic. The proposed technique utilises high density programmable logic devices (PLDs) to realise DSP structures that can be rapidly reconfigured in the field. A complete development system, consisting of a suite of computer-aided design tools, has been developed to provide the DSP designer with the means of generating hardware solutions in a short period of time. The work presented here covers all types of IIR and FIR digital filters, however, further work is continuing to include other DSP structures.< >

关键词： Application specific integrated circuits Design automation Digital filters Digital signal processors Logic arrays

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field-programmable gate-arrays and semi-custom designs for sinusoidal and current-regulated PWM

Field-programmable gate-arrays and semi-custom designs for s...

引用

iee colloquium on ASIC technology for Power Electronics Equipment

作者： T.C. Green M. Mirkazemi-Moud J.K. Goodfellow B.W. Williams Department of Electrical and Electronic Engineering Heriot-Watt University Edinburgh UK Ling Dynamic Systems UK Limited Royston Hertfordshire UK

Reductions in the size of power electronic equipment brought about by improved devices and packaging technology can now be matched even at moderate sales volumes by smaller control circuits employing ASICs. A digital ASIC is used to replace a microprocessor in a sinusoidal PWM system. An encoded look-up table is used to greatly reduce the silicon area required and hence reduce costs. A mixed technology ASIC is used to implement high-frequency, current-regulated PWM in a digital format with an on-chip analogue interface. This brings advantages over its all-analogue pre-cursor in terms of reduced calibration, better repeatability, precisely controllable modes of operation and lower component costs. field-programmable gate-arrays were used for proving design concepts and testing chip performance in the complete system before committing designs to silicon, thereby saving time and costs during development and allowing greater opportunities for evaluation of the designs.< >

关键词： Application specific integrated circuits Cellular logic arrays Logic arrays Power electronics Pulse width modulation Table lookup

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Adaptive hardware becomes a reality using electrically reconfigurable arrays (ERAs)

Adaptive hardware becomes a reality using electrically recon...

引用

iee colloquium on User-Configurable Logic - technology and applications

作者： P. Dillien GEC Plessey Semicond. Swindon UK

Reconfigurable systems-which modify their operation to adapt to prevailing conditions-promise new and exciting design concepts for the 1990s. Adaption, to date, has primarily been the domain of software, but new hardware techniques of logic design using RAM based silicon open up significant benefits. The author discusses how the Electrically Reconfigurable arrays (ERAs) can be used in adaptive hardware systems. The generic name of SRAM based products such as the ERA is field programmable gate arrays (FPGAs). Key features to look for in FPGAs for adaptive hardware applications are speed and flexibility of reconfiguration.< >

关键词： Logic arrays Logic design

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Electrically reconfigurable arrays-ERAs

Electrically reconfigurable arrays-ERAs

引用

iee colloquium on New Directions in VLSI Design

作者： P. Dillien

Plessey Semiconductors Ltd. have recently introduced a novel type of programmable Logic Device categorised as field programmable gate arrays (FPGAs). Offering exciting opportunities for FPGA applications, the devices are known as Electrically Reconfigurable arrays-ERAs. ERAs allow the user to design and programme devices in their own premises resulting in short design and production lead times with no NRE charges. These features make the devices viable for small production runs and the natural choice of technology where frequent production variations are required to meet specific customer needs.< >

关键词： Application specific integrated circuits Logic arrays

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