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检索条件"任意字段=IEE Colloquium on Field Programmable Gate Arrays - Technology and Applications"

共 52 条记录，以下是41-50 订阅

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FPGA implementation of the timing synchronization in preamble based OFDM system

FPGA implementation of the timing synchronization in preambl...

引用

iee Mobility Conference 2005 - The Second International Conference on Mobile technology, applications and Systems

作者： Gu, Y.J. Li, Y. Ren, W. Chen, K.S. Zhejiang University Hangzhou China

ISBN: (纸本)9810545711

Orthogonal frequency division multiplexing (OFDM) is an effective modulation technique for high-rate transmission over frequency selective fading channels. However, just because of its orthogonality, OFDM systems are also extremely sensitive and vulnerable to synchronization errors. In this paper, we investigate a scheme especially for symbol synchronization utilizing the special training structure, which can be used in preamble-based OFDM system. Without loss the generality, ieeE 802.11a WLAN system will be researched as the model. The algorithms of match filter and cyclic prefix (CP) are combined to achieve good symbol timing synchronization. The former algorithm is to determine the short training symbol's precise end of the burst transmission, and then the latter algorithm will confirm the valid data of data symbols. At last, we present the timing synchronization's FPGA implementation.

关键词： field programmable gate arrays (FPGA)

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New partitioning technology permits FPGA prototypes

New partitioning technology permits FPGA prototypes

引用

iee colloquium on Fast Prototyping of IC Designs

作者： D. Pashley D. Brasen G. Saucier Direct Insight Limited Brackley Northamptonshire UK I.N.P.G/CSI Grenoble France Innovative Synthsis Technologies Danville CA USA

In this paper, a new package partitioning tool from Innovative Synthesis Technologies is described that uses functional cone partitioning (ICCAD93) to find high size to I/O ratio partitions. Partitioning for performance is provided by containing whole critical paths within packages, made easy with functional cone partitioning. Hierarchy is respected, allowing for partitioning into heterogeneous devices. As an extension of the ASYL+ netlist synthesis and technology migration system, the tool partitions for multiple PLD, FPGA, and ASIC technologies for desired market price and performance.< >

关键词： Application specific integrated circuits Design automation field programmable gate arrays Integrated circuit packaging Logic partitioning programmable logic devices

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gate array implementation of the composite radix transform algorithm

Gate array implementation of the composite radix transform a...

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iee colloquium on Signal Processing applications of Finite field Mathematics

作者： B. Daniel R. Phillips GEC Avionics Limited USA

Describes the development of two application specific integrated circuit devices which, together, form the basis of a high performance, modular Fourier transform processor. The processing algorithms employed within these devices were devised by T. Curtis (see ibid., no.1989/90, p.2/1-9, 1989) of the Admiralty Research Establishment, Portland. From the initial formulation of the prime radix transform (PRAT) algorithm and the exploitation of emerging gate array technology, the final system design was developed through a series of refinements to both the algorithms and the hardware implementation. As part of this process, the original algorithms were extended to allow for the inclusion of non-prime number transforms; giving rise to the formulation of the composite radix fourier transform (CRAFT) algorithm. An outline is given of the algorithms used, and their method of partitioning and implementation within the two devices.< >

关键词： Application specific integrated circuits Cellular logic arrays Discrete Fourier transforms

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Exploiting real-time FPGA based adaptive systems technology for real-time sensor fusion in next generation automotive safety systems

Exploiting real-time FPGA based adaptive systems technology ...

引用

iee Seminar on Target Tracking: Algorithms and applications

作者： Chappell, Steve Macarthur, Alistair Preston, Dan Olmstead, Dave Flint, Bob Sullivan, Chris Celoxica Ltd 66 Milton Park Abingdon Oxfordshire OX14 4RX United Kingdom Medius Inc. 911 Western Ave Seattle WA 98104 United States BAE SYSTEMS Ventures Warwick House Aerospace Centre Farnborough GU14 6YU United Kingdom

ISBN: (纸本)086341608X

We present a system for the boresighting of sensors using inertial measurement devices as the basis for developing a range of dynamic real-time sensor fusion applications. The proof of concept utilizes a COTS FPGA platform for sensor fusion and real-time correction of a misaligned video sensor. We exploit a custom-designed 32-bit soft processor core and C-based design & synthesis for rapid, platform-neutral development. Kalman filter and sensor fusion techniques established in advanced aviation systems are applied to automotive vehicles with results exceeding typical industry requirements for sensor alignment. Results of the static and the dynamic tests demonstrate that using inexpensive accelerometers mounted on (or during assembly of) a sensor and an Inertial Measurement Unit (IMU) fixed to a vehicle can be used to compute the misalignment of the sensor to the IMU and thus vehicle. In some cases the model predications and test results exceeded the requirements by an order of magnitude with a 3-sigma or 99% confidence. © Celoxica Ltd.

关键词： field programmable gate arrays (FPGA)

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Hardware implementations of algorithms on networks of FPGA processors

Hardware implementations of algorithms on networks of FPGA p...

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iee colloquium on Digital System Design Using Synthesis Techniques (Digest No: 1996-029)

作者： S.J.B. Acock K.R. Dimond

The reduction in size of features of integrated circuits means that a massive number of gates can be accommodated on a single device. In specific applications significant processing capacity can be incorporated into individual application specific integrated circuits. However, there will be many instances when such devices are not suitable, either due to performance considerations or flexibility requirements. A part of the resources of an application specific integrated circuit will not be used in processing but in offering user programmability. Clearly it would be possible to realise more substantial processing structures within a device if they were implemented within more flexible building blocks. This paper describes the work that is underway at the University of Kent to develop a flexible system based on FPGA devices for implementing algorithms described using VHDL.

关键词： field programmable gate arrays

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Principal Component Analysis Approach in Selecting Type-1 and Type-2 Fuzzy Membership Functions for High-dimensional Data 17

Principal Component Analysis Approach in Selecting Type-1 an...

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Joint 17th World Congress of International-Fuzzy-Systems-Association / 9th International Conference on Soft Computing and Intelligent Systems (IFSA-SCIS)

作者： Raj, Desh Gupta, Aditya Tanna, Kenil Garg, Bhuvnesh Rhee, Frank Chung-Hoon Indian Inst Technol Guwahati Dept Comp Sci & Engn Gauhati 781039 India Indian Inst Technol Guwahati Dept Math Gauhati 781039 India Hanyang Univ Dept Elect & Commun Engn Ansan 15588 South Korea

ISBN: (纸本)9781509049172

With increased interest in learning from data, algorithms that manipulate datasets containing hundreds of features have become popular in various fields such as medicine, image processing, geolocation, biochemistry, and computational linguistics. Since a number of these applications exploit the power of fuzzy sets in representing uncertainties, it may be considered essential to describe a method for selecting the most suitable fuzzy membership function to represent a high-dimensional dataset. In this paper, we propose such a method, which is based on dimensionality reduction using the Principal Component Analysis (PCA) technique, followed by the Wilcoxon Minimal Bin Size algorithm, which has earlier been evaluated on multidimensional datasets up to 8 dimensions. We further demonstrate our proposed method using two real datasets consisting of 281 and 500 features, respectively.

关键词： Estimation field programmable gate arrays OFDM Modulation Filtration Clocks Signal processing algorithms

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VHDL simulation of peak detector, 64 bit BCD counter and reset automatic block for PD detection system using FPGA

VHDL simulation of peak detector, 64 bit BCD counter and res...

引用

International colloquium on Signal Processing & Its applications, CSPA

作者： Emilliano Chandan Kumar Chakrabarty Ahmad Basri A. Ghani Agileswari K. Ramasamy Department of Electronics and Communication Engineering College of Engineering Universiti Tenaga Malaysia (UNITEN) Selangor Darul Ehsan Malaysia

ISBN: (纸本)9781424471218

Currently, FPGA (field programmable gate Array) technology is being widely used for accelerator control owing to its fast digital processing capability. This paper is purely a model to determine the design circuit to implement Partial Discharge (PD) detection in FPGA technology. The research shall involve ISE Simulator version 9.2i (Xilinx) and Very high integrated circuit Hardware Description Language (VHDL) programming to evaluate the use of field Programming gate Array (FPGA) for the detection and counting of partial discharge signals in underground cable. The impulse signals at the input data have very fast rise time in the range of 1 ns to 2 ns. The impulse signals will be processed, detected and counted using ADC with peak detector block, counter with reset block and reset automatic block.

关键词： Counting circuits field programmable gate arrays Partial discharges Radiation detectors Signal processing Acoustic signal detection Signal synthesis Signal detection Probes Latches

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Reconfigurable DSP systems

Reconfigurable DSP systems

引用

iee colloquium on applications Specific Integrated Circuits for Digital Signal Processing

作者： M.A. Wahab D.J. Puckey Department of Electronics and Information Technology University of Glamorgan Mid-Glamorgan UK Dept. of Electron. & Inf. Technol. Glamorgan Univ. Pontypridd UK

Presents a new approach to the implementation of DSP structures that combines many of the benefits of ASIC-based systems with those of DSP processors. It is part of the work that the authors are engaged in to design and implement efficient DSP structures using hard-wired logic. The proposed technique utilises high density programmable logic devices (PLDs) to realise DSP structures that can be rapidly reconfigured in the field. A complete development system, consisting of a suite of computer-aided design tools, has been developed to provide the DSP designer with the means of generating hardware solutions in a short period of time. The work presented here covers all types of IIR and FIR digital filters, however, further work is continuing to include other DSP structures.< >

关键词： Application specific integrated circuits Design automation Digital filters Digital signal processors Logic arrays

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An FPGA-based implementation of variable fractional delay filter

An FPGA-based implementation of variable fractional delay fi...

引用

International colloquium on Signal Processing & Its applications, CSPA

作者： Ussanai Nithirochananont Sorawat Chivapreecha Kobchai Dejhan Department of Telecommunications Engineering Faculty of Engineering King Mongkut''s Institute of Technology Ladkrabang Bangkok Thailand

A variable fractional delay (VFD) filter is widely used in applications such as symbol timing recovery, arbitrary sampling rate conversion and echo cancellation. This paper presents an implementation of variable fractional delay filter on FPGA. The implementation utilizes an efficient structure so called Taylor structure. The main advantage of this structure is to reduce number of multiplier and adder when compared with Farrow structure or modified Farrow structure. The result of implementation will be reported as throughput and area utilization.

关键词： Finite impulse response filter field programmable gate arrays Delay effects Lagrangian functions Interpolation Arithmetic Transfer functions Timing Echo cancellers Throughput

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Xilinx FPGA design in a group environment using VHDL and synthesis tools

Xilinx FPGA design in a group environment using VHDL and syn...

引用

iee colloquium on Digital System Design Using Synthesis Techniques (Digest No: 1996-029)

作者： C.G. Harrison P.L. Jones Division of Electrical Engineering The Manchester School of Engineering University of Manchester Institute of Science and Technology Manchester UK

The use of VHDL and synthesis tools has been shown to be well suited to achieving the objectives in a group design environment. The expressiveness of VHDL lends itself to group discussion and with synthesis, the outcome is correct by construction and can be verified rapidly in a true system environment built around a Xilinx FPGA. Not surprisingly however since this year has seen the first full run of students through the course there have been problems. Students in their second year are not sufficiently mature to accept that fighting the CAD system and winning is a necessary part of becoming a successful designer and so they complain continually about the apparent dumbness of Autologic, its slowness and its seemingly obscure error messages. The complaints about the VHDL compiler run in a similar vein. Perhaps one day CAD tools of this complexity really will become quicker and less hostile. However, what this year's group cannot appreciate is how much more productive and successful they have been than have several years of preceding cohorts using traditional design methods with schematic capture. More help will of course be available on how to write VHDL to achieve more efficient synthesis as more experience is gained by staff of the seemingly infinite set of traps waiting to catch the novice designer.

关键词： field programmable gate arrays

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