Embedded Block Coding with Optimized Truncation (EBCOT) algorithm plays a basic and crucial part in JPEG2000 still image compression system. This paper proposes a VLSI architecture of EBCOT, in which a Dynamic Memory ...
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(纸本)078037889X
Embedded Block Coding with Optimized Truncation (EBCOT) algorithm plays a basic and crucial part in JPEG2000 still image compression system. This paper proposes a VLSI architecture of EBCOT, in which a Dynamic Memory Control (DMC) strategy is used to reduce 60% scale of the on-chip wavelet coefficients storage. A parallel architecture is proposed to speed-up the coding process. This architecture can be used as a compact and efficient IP core for JPEG2000 VLSI implementation and various real-time image&video applications.
The Euclidean distance transform (EDT) is an important tool in image analysis. Previous work on computation of EDT is limited to sequential algorithms and parallel algorithms on general purpose architectures. The auth...
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The Euclidean distance transform (EDT) is an important tool in image analysis. Previous work on computation of EDT is limited to sequential algorithms and parallel algorithms on general purpose architectures. The authors develop a fast parallel algorithm that is amenable for VLSI implementation. The VLSI architecture is presented. Results of implementation of the VLSI design in a commercial package are also presented, and confirm the speed and suitability of the new method for real-time applications.
In this paper, we have designed an efficient parallel algorithm for performing 3 D image reconstruction. In our framework, we have considered 3 D image to be reconstructed from a series of 2 D images, produced using U...
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In this paper, we have designed an efficient parallel algorithm for performing 3 D image reconstruction. In our framework, we have considered 3 D image to be reconstructed from a series of 2 D images, produced using Ultrasonography, Computer Tomography, etc. The paper discusses a general parallel algorithm for 3 D image reconstruction over CRCW, CREW and EREW PRAM models. We have developed efficient implementations of this algorithm over a vector machines, a distributed system comprising of a cluster of Work Stations and various interconnection network like mesh network and reconfigurable bus network. The performance of the above algorithms are tested using simulation experiments performed for 3 D image reconstruction of the vitreous region of the eye using ophthalmic ultrasonograms. A novel approximation scheme has also been proposed for a drastic improvement in performance for specific kinds of image. Results indicate the time complexities of the algorithms are in resonance with expected theoretical values and image obtained has a uncompromising level of accuracy.
The DAP Gamma II is a single instruction multiple data (SIMD) computer of either 1024 or 4096 processors which can be used as a component in a real-time system. The DAP can be programmed in a mix of high level languag...
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The DAP Gamma II is a single instruction multiple data (SIMD) computer of either 1024 or 4096 processors which can be used as a component in a real-time system. The DAP can be programmed in a mix of high level languages (Fortran Plus and C++), low level languages, and library functions. For easy development and signal applications, there is also a development system based on Khoros. Various high-speed I/O interfaces are supported, however, the DAP contains a sufficiently large memory to allow sequences of whole-image operations to be performed without any intermediate I/O.
This paper presents the design of a general-purpose, real-time imageprocessing architecture, required for developing proof of principle demonstrations of military imageprocessingapplications. The main requirements ...
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This paper presents the design of a general-purpose, real-time imageprocessing architecture, required for developing proof of principle demonstrations of military imageprocessingapplications. The main requirements of the architecture are to provide a scaleable, modular parallelprocessing framework, with very high bandwidth (at least 64 MByte s-1) point to point interprocessor communications. The architecture is heterogeneous, and a particular combination of processors may be chosen according to the application. A strong emphasis has been placed on the use of open standards, both for the hardware and software, and, where possible, COTS products are used.
The paper presents an interactive segmentation system that uses a parallelprocessing architecture. Poor contrasts, variable tissue properties and complex-shaped structures make the isolation of meaningful regions of ...
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The paper presents an interactive segmentation system that uses a parallelprocessing architecture. Poor contrasts, variable tissue properties and complex-shaped structures make the isolation of meaningful regions of interest difficult. The interactive approach uses the human user's knowledge base to assist in image segmentation. The measurement of regions of interest enable the resultant output image to be quantified for clinical purposes. The graphical user interface - developed under Microsoft Windows - incorporates a mouse driven interactive display. A transputer based parallelprocessing engine is provided for the computationally intensive tasks of the system. These modules of the system communicate with each other using the Windows Dynamic Data Exchange (DDE) model.
There is an increasing number of applications of automated image analysis in which imaging is part of an instrumentation or process control system. Such embedded applications often require performance to be tuned in v...
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There is an increasing number of applications of automated image analysis in which imaging is part of an instrumentation or process control system. Such embedded applications often require performance to be tuned in various ways to satisfy time constraints, which may vary through the lifetime of the application. They may be a requirement to produce versions of an imaging product targeted at different classes of user, to satisfy various market niches. It is important to develop software tools to easily target a variety of computational engines. The application of hardware compilation technology in a field programmable gate array (FPGA)-based system to some typical imageprocessing tasks is presented.
Optical flows (OF) have achieved greater accuracy over large speeds by improvements in implementation. Unfortunately, the improvements require the processing of more image frames or larger spatial regions. General-pur...
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Optical flows (OF) have achieved greater accuracy over large speeds by improvements in implementation. Unfortunately, the improvements require the processing of more image frames or larger spatial regions. General-purpose multicomputers can be deployed to reduce the timings recorded on workstations either in algorithmic development work or in repeatedly finding the OF field over many sets of image sequences. Four methods are parallelized but are not unusual amongst the OF methods in being amenable to data-farming. parallelizing a number of routines in a systematic manner is possible if a generalized framework is available like what is provided by the pipelined processor farming (PPF) methodology and knowledge of common structure to OF methods.
A 64-bit computer processor architecture capable of performing a maximum of eight instructions per cycle, but with an instruction word much shorter, is presented. These performances are obtained through the addressing...
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A 64-bit computer processor architecture capable of performing a maximum of eight instructions per cycle, but with an instruction word much shorter, is presented. These performances are obtained through the addressing of 128 registers storing the most frequently executed instructions. It is shown that the drawback of the instruction register file (IRF) initialization is not significant for digital signal processingapplications. In combination with a high-speed external memory, this operation is even much faster than the instruction cache initialization necessary in every traditional very long instruction word (VLIW) architecture. For this reason, indirect reduced instruction set computing represents a solution for extending the application of VLIW.
This paper presents the design of a general-purpose, real-time imageprocessing architecture, required for developing proof of principle demonstrations of military imageprocessingapplications. The main requirements ...
This paper presents the design of a general-purpose, real-time imageprocessing architecture, required for developing proof of principle demonstrations of military imageprocessingapplications. The main requirements of the architecture are to provide a scaleable, modular parallelprocessing framework, with very high bandwidth (at least 64 MByte s/sup -1/) point to point interprocessor communications. The architecture is heterogeneous, and a particular combination of processors may be chosen according to the application. A strong emphasis has been placed on the use of open standards, both for the hardware and software, and, where possible, COTS products are used.
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