British Aerospace (Space Systems) Ltd. is currently developing an integrated digital signal and imageprocessing architecture for the European Space Agency. It is intended that this multiprocessor architecture will be...
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British Aerospace (Space Systems) Ltd. is currently developing an integrated digital signal and imageprocessing architecture for the European Space Agency. It is intended that this multiprocessor architecture will become an open system standard for demanding space-based applications. The architecture is also directly applicable to many ground-based imageprocessingapplications. This paper presents the rationale behind the development of the integrated DSP/IP architecture and describes the various facets of the architecture (interprocessor communications, processing elements and control philosophy).< >
Describes the architecture of the ELSA Processor, a massively parallel SIMD/MSIMD machine implemented in wafer scale technology, and its capability to implement many algorithms in imageprocessing, pattern recognition...
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Describes the architecture of the ELSA Processor, a massively parallel SIMD/MSIMD machine implemented in wafer scale technology, and its capability to implement many algorithms in imageprocessing, pattern recognition, signal processing, etc. The ELSA Processor contains 2304 bit serial processing elements (PEs) configured in a two dimensional array. The wafer employs a 1.2 mu m double metal CMOS process and will operate at a clock speed of up to 20 MHz. For eight bit data, additions can be carried out at about 5 billion per second.< >
A transputer network is used for visual texture analysis. The image is segmented and farmed amongst the transputers of the network. The analysis is based on fractal texture measurements, modified to be suitable for no...
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A transputer network is used for visual texture analysis. The image is segmented and farmed amongst the transputers of the network. The analysis is based on fractal texture measurements, modified to be suitable for non-fractal visual texture from natural scenes. Gravity feed dynamic load-balancing is used for data distribution, with software written in a modular fashion to facilitate changes in topology. Various array and tree topologies are evaluated and compared. Timing comparison is used to identify and eliminate bottlenecks and 94% efficiency is achieved using an array of 16 slave transputers.< >
parallelarchitectures have yet to achieve the generality of sequential processing, particularly in areas such as imageprocessing and vision. The main reason why parallelprocessing does not exhibit the same generali...
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parallelarchitectures have yet to achieve the generality of sequential processing, particularly in areas such as imageprocessing and vision. The main reason why parallelprocessing does not exhibit the same generality as sequential processing is because a large number of new degrees of freedom have been introduced for both the compiler writer and programmer. They include class of architecture, topology, programming paradigm reconfiguration, and the number of processors to be used. The complex relationship between these factors in typical real-time vision applications, makes performance estimation almost impossible and thus encourages a heuristic design philosophy. The authors approach is to fix some of these degrees of freedom to constrain the parallel architecture so that performance estimation is feasible. In this paper it is shown that, although not optimal in all areas, tree topologies of distributed processors with point-to-point communication links (e.g. the transputer) offer the best compromise between generality, performance and cost.< >
An architecture of a dynamically reconfigurable, multidimensional multidirectional parallel pipelined (M/sup 2/P/sup 2/) system is presented for real time imageprocessingapplications. It is implemented as a chain of...
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An architecture of a dynamically reconfigurable, multidimensional multidirectional parallel pipelined (M/sup 2/P/sup 2/) system is presented for real time imageprocessingapplications. It is implemented as a chain of interconnected modules, each having high performance TMS320c25 processing elements (PEs). These PEs can be configured to operate as independent stages of a single pipeline or grouped into two or four multiprocessor pipeline stages. Also, different stages need not comprise an equal number of PEs. Rather, each stage is configured according to the processing requirement of that stage. This results in a highly efficient pipeline structure having optimum task division. The configuration of pipeline stages can be done under software control.< >
Many applications of artificial-vision systems are complex and computationally expensive and so demand powerful and therefore expensive processing units. However, there is also a place for low-cost systems. Artificial...
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Many applications of artificial-vision systems are complex and computationally expensive and so demand powerful and therefore expensive processing units. However, there is also a place for low-cost systems. Artificial vision systems for use in manufacturing industry may need high speed response, but not all manufacturing applications do. High resolution is sometimes needed, but often working with low-resolution images can give useful results. Cost is often of great importance with systems to be used in manufacturing. The paper describes the early stages of an investigation into multi-processor systems for image-processing which do not involve large expenditure.< >
The design of motion video image compression algorithms has been a very time consuming process when carried out with the aid of serial computers. Without real-time or near real-time simulation aids it is difficult and...
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The design of motion video image compression algorithms has been a very time consuming process when carried out with the aid of serial computers. Without real-time or near real-time simulation aids it is difficult and tedious to assess the performance of different algorithms. Recently the CCITT set an international standard for motion video codecs, H.261, which took several years to develop. The authors address the problem of such software simulations. Here they discuss speeding up simulations by the use of a concurrency.< >
An image coder, based on the CCITT H261 recommendation for real-time coding and decoding of moving video images, is presented. The coded images include a minor departure from the H261 recommendation as the transmissio...
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An image coder, based on the CCITT H261 recommendation for real-time coding and decoding of moving video images, is presented. The coded images include a minor departure from the H261 recommendation as the transmission of video conferencing images is intended for a LAN (Local Area Network) environment. This project extends the coding algorithms to include video images. A secondary objective is the modification of the algorithms to conform precisely to an ISDN transmission environment. The process of implementing the algorithms in occam on a transputer network is discussed. The problems encountered in this process are highlighted, and methods to increase performance are presented.< >
A hybrid architecture for machine vision is described. The primary components of the architecture are a Datacube pipelined image processor, a configurable network of 32 T800 transputers, a Sun-4 workstation and a spec...
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A hybrid architecture for machine vision is described. The primary components of the architecture are a Datacube pipelined image processor, a configurable network of 32 T800 transputers, a Sun-4 workstation and a special-purpose interface connecting the Datacube to the transputer network. The implementation of a 3D structure-from-motion vision algorithm (Droid) on this architecture is described. This algorithm reconstructs 3D structure by analysing image sequences obtained from a moving camera. The Datacube handles the image digitisation, storage and display; the transputer network performs the feature extraction (corner points) in parallel and the Sun-4 computes the 3D-isation. In this application, which was demonstrated live during a recent ESPRIT conference in Brussels, the architecture delivers a performance of greater than 1 frame per second-17 times the performance of a Sun-4 alone.< >
image compression algorithms based on block transform coding have been adopted by the CCITT for coding of visual telephony. Recent developments in block transform coding show that by incorporating adaptive blocksizes,...
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image compression algorithms based on block transform coding have been adopted by the CCITT for coding of visual telephony. Recent developments in block transform coding show that by incorporating adaptive blocksizes, the efficiency in terms of bit-rate and subjective image quality of such coding methods are improved. The characteristics of this Scene Adaptive Transform Coding algorithm are introduced. The computational intensity and highly parallel nature of such algorithms motivate the use of a multiple processor network to execute the algorithms in close to real-time. The authors reveal a method to exploit a second degree of parallelism which aims to further increase the efficiency of the network. This second degree of concurrency is achieved by parallelising the functional algorithms. Pipelining methods are used to exploit the functional concurrency within the algorithms. By maintaining a suitable granularity of data partitioning and parallelising the functional algorithms, a balance in the computation to communication on multiprocessors can be achieved. The performance of the proposed Pipeline-Tree Architecture (PTA) is compared with the commonly used Tree structure.< >
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