Most recently, an area based region growing stereo matcher (Otto & Chau 1989) using an adaptive least-squares correlation was developed by the Alvey MMI-137 project. This algorithm (coded in C) is being used as th...
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Most recently, an area based region growing stereo matcher (Otto & Chau 1989) using an adaptive least-squares correlation was developed by the Alvey MMI-137 project. This algorithm (coded in C) is being used as the second step in a completely automated system for extracting 3D co-ordinates of terrestrial and industrial surfaces from stereo images, the first step is being the extraction of some conjugate points 'seed points' in the two stereo images (Allison, Zemerly and Muller 1991). This stereo matcher requires about six days (cpu) for a full sized 6000*6000 pixel SPOT pair processed serially on Sun sparcstations running SunOS. The objective of this work is to match these pairs in about two hours using the PARSYS SN1000 (48 T800+4MB-RAM) Supernode based transputer machine.< >
Adaptability and high performance are prerequisites for cost-effective automatic industrial inspection and other product handling systems. The specification of appropriate systems therefore demands the development bot...
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Adaptability and high performance are prerequisites for cost-effective automatic industrial inspection and other product handling systems. The specification of appropriate systems therefore demands the development both of high performance algorithms and efficient techniques for implementation, together with a means of matching algorithms and implementational infrastructure. Transputer arrays offer a potentially very effective infrastructure for the implementation of pattern classification algorithms, which often embody inherent parallelism in their structure. The paper investigates ways in which a number of classification algorithms, particularly those directly optimised for the processing of binary images and applicable to automatic inspection tasks, can be mapped to an array of transputers to provide a real-time environment for classification processing. It is shown how the parallel implementation of a multilevel hierarchical architecture can offer significant benefits in defining the relationship between computational complexity (and therefore attainable processing speeds) and error rate performance.< >
With the advent of parallelprocessing redundancy, in the form of multiple microprocessors is automatically available. There is now much interest in trying to exploit this redundancy for fault tolerance while at the s...
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With the advent of parallelprocessing redundancy, in the form of multiple microprocessors is automatically available. There is now much interest in trying to exploit this redundancy for fault tolerance while at the same time utilising the increased processing power. In such systems dynamic reconfiguration and graceful degradation can be employed presenting many interesting challenges to system developers. In the article the experiences of developing these systems using transputers for safety-critical real-time control systems is discussed. Although the work highlights aircraft applications many of the ideas proposed can be translated to other application areas.< >
Describes the MasPar MP-1 architecture and thereby demonstrates its potential for very high-performance; Describes MasPar's programming tools and environment; and illustrates the benefits obtained in porting appli...
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Describes the MasPar MP-1 architecture and thereby demonstrates its potential for very high-performance; Describes MasPar's programming tools and environment; and illustrates the benefits obtained in porting applications packages on to MasPar computers. In describing these features the ease of programming and the realisation of very high performance for real applications is demonstrated.< >
When implemented digitally, large-scale audio processing systems require the realisation of highly parallelarchitectures. Task scheduling strategies are necessary to distribute the processing algorithms required-term...
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When implemented digitally, large-scale audio processing systems require the realisation of highly parallelarchitectures. Task scheduling strategies are necessary to distribute the processing algorithms required-termed the taskforce-across such architectures. The results obtained show that good-quality solutions can be expected from simple heuristic methods with minimum scheduling overhead. More advanced heuristic policies demonstrate particular promise for fast near-optimal re-allocation of processing resources in real-time audio processingapplications.< >
The binary Hough transform (BHT) as well as its implementation and applications to visual inspection have been briefly presented and discussed. It has been verified that it provides some interesting features and could...
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The binary Hough transform (BHT) as well as its implementation and applications to visual inspection have been briefly presented and discussed. It has been verified that it provides some interesting features and could be an effective option for application in visual inspection and to produce the representation of the digital images by endpoints of its straight line segments to be used for posterior higher level recognition. Its fast execution in software and hardware makes it an interesting option for real time applications. Further developments being addressed by the authors include: theoretical analysis of the BHT accuracy and effectiveness, bit-level versions of the BHT systolic architectures, a hierarchical BHT, a BHT based on trivial line segments, application of the BHT to image compression and the usage of the BHT systolic architectures for other DSP and imageprocessing tasks (e.g. filters, convolvers).< >
In many engineering applications, the numerical solution of partial differential equations is required in the design and simulation of new products. Typically the speed and accuracy of such simulations have to be comp...
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In many engineering applications, the numerical solution of partial differential equations is required in the design and simulation of new products. Typically the speed and accuracy of such simulations have to be compromised by the user because of the limitations in computer power, resources and memory. As serial computers reach fundamental limits in performance, many engineers are turning to parallel computers to provide them with the computing power necessary for their design work. The iPSC/860 family of concurrent supercomputers gives the design engineer the computer power and memory for fast and accurate simulations. The iPSC/860 contains a number of processors or 'nodes', each with their own local memory. Calculations are carried out on data in a processor's local memory and data can be transferred between processors' local memory by message passing. There is no shared memory or shared resources to limit the scalability of the system.< >
The authors have developed binary optical logic planes, based on nonlinear interference filters, and used them to construct basic demonstration optical processing systems. The logic planes are based on thermally sensi...
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The authors have developed binary optical logic planes, based on nonlinear interference filters, and used them to construct basic demonstration optical processing systems. The logic planes are based on thermally sensitive dielectric interference filters with external absorbers, known as BEAT devices (bistable etalons with absorbed transmission). They are operated as three-port gates. The processing scheme currently explored derives from the (electronic) cellular logic image processor. It consists of a parallel optical coprocessor operating in single instruction multiple data stream mode, controlled by a conventional electronic host computer. By programming both the Boolean logic operations carried out in the processing unit and the responses of the threshold unit on each cycle, a wide range of binary imageprocessing functions can be built up over a number of iterations using a system of this type.< >
This colloquium contains 9 articles on the use of transputer and other architectures. Topics covered include: real-time control of high-speed machines, transputer hardware and software for a multimanipulator robotic e...
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This colloquium contains 9 articles on the use of transputer and other architectures. Topics covered include: real-time control of high-speed machines, transputer hardware and software for a multimanipulator robotic environment;parallel methodologies for large-scale simulation;applications of transputers to aircraft simulation and control and real-time simulation and control of power systems.
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