A description is given of a class of exact least-squares algorithms based on a modular structure, known as the multistage lattice predictor and an efficient means of implementing these algorithms in parallel on an arr...
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A description is given of a class of exact least-squares algorithms based on a modular structure, known as the multistage lattice predictor and an efficient means of implementing these algorithms in parallel on an array of transputers. These algorithms are known collectively as least-squares lattice (LSL) algorithms, involving both order update and time update recursions. Lattice algorithms are robust, being insensitive to variations in the eigenvalue spread of the correlation matrix of the input data and have a computational cost that increases linearly with the number of adjustable tap weights. The authors derive an efficient systolic array structure for the multi-channel least-squares lattice algorithm and demonstrate how the inherently parallel systolic structure can be mapped onto a transputer array.< >
A fully automatic vision-based technique to extract traffic data from scenes of roadway is proposed. This involves the application of a scene analysis technique to find, identify and determine the coordinates of movin...
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A fully automatic vision-based technique to extract traffic data from scenes of roadway is proposed. This involves the application of a scene analysis technique to find, identify and determine the coordinates of moving vehicles and pedestrians in each frame. The coordinates/time data are translated into a number of traffic flow parameters. A number of detection and tracking algorithms are implemented in the OCCAM language to run on a transputer-imageprocessing system. The application of the MAT-transform as an aid for vehicle classification is investigated. The initial results are discussed.< >
An ever increasing amount of map data for the world's land masses is held in digital format. The computational demands of producing images in an acceptable time can be met by using high performance and low cost pa...
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An ever increasing amount of map data for the world's land masses is held in digital format. The computational demands of producing images in an acceptable time can be met by using high performance and low cost parallelprocessing machines so that new algorithms can be rapidly prototyped and tested. Such an approach has been made feasible by the use of transputer systems. There are a number of conventional algorithms which take digital surface data and process it to produce the required images. Most current algorithms are inherently sequential and do not, in general, map easily onto parallel processor architectures. The authors show that by careful algorithm design the problem can be mapped onto a number of processors by exploiting the fact that a calculation for one area is not dependent on any other data manipulations other than its own and hence can proceed independently. The algorithm is based on ray casting.< >
The IMS B420 (Vectram) has been developed to offer both scalar and vector processing in a single 'TRAM' module. This module combines the scalar floating/integer and the general purpose capabilities of the tran...
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The IMS B420 (Vectram) has been developed to offer both scalar and vector processing in a single 'TRAM' module. This module combines the scalar floating/integer and the general purpose capabilities of the transputer with a high performance vector/signal processing co-processor. A set of software libraries are available which allow programs, written in high level languages, running on the transputer to call vector routines executed on the coprocessor. The author summarises the Vectram architecture and its principle of operation. The nature of the support software and some application areas are also discussed.< >
A hybrid parallel and sequential architecture may be the optimum solution to the calculation of the FFT. The authors have constructed such a system consisting of three TMS 320C25 digital signal processors. Two of the ...
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A hybrid parallel and sequential architecture may be the optimum solution to the calculation of the FFT. The authors have constructed such a system consisting of three TMS 320C25 digital signal processors. Two of the processors work in parallel, performing 256-point radix-4 decimation in frequency 'in place' complex FFTs. The third processor combines the outputs of the other two processors thus forming the full 512-point FFT. It also performs the unscrambling of the data from the preceding processors and the digit reverse procedure prior to outputting the results. The system has been constructed on two IBM PC/AT plug-in cards with the interfacing to the IBM being carried out via its I/O ports.< >
Robot techniques appear to have made little impact on applications areas involving part assembly. This is mainly due to a lack of flexibility and consequent problems of cost justification, particularly where there are...
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Robot techniques appear to have made little impact on applications areas involving part assembly. This is mainly due to a lack of flexibility and consequent problems of cost justification, particularly where there are multiple products and short production runs. Ways of increasing flexibility include the reduction of fixturing by using more than one robot on an assembly task, the provision of enhanced sensing capabilities by using multiple sensors, and the use of the sensory system to provide information for an error correction and detection facility. A complex system with these facilities places particular emphasis on the requirement to integrate a set of subsystems. This integration is difficult to achieve using conventional methods of computer control. To overcome these problems a vertically integrated architecture has been developed in which the integration concepts are carried through from the algorithms to a parallelprocessing implementation. The approach is based upon the asynchronous coordinated action of many agents and gives rise to the concept of a societal architecture-a society of agents. The structure of the agents and the manner in which information is passed between them is heavily influenced by the need to support a large number of simple agents and by the need to achieve real time operation. This latter can be achieved by an architecture, Vortex, which is based on the concept of dynamic shared data.< >
Most literature on fractals defined by self-affine systems (SASs) assume that Monte Carlo methods will be used for rendering the attractor. These are so inefficient as to be unsuitable for use in decompressing fractal...
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Most literature on fractals defined by self-affine systems (SASs) assume that Monte Carlo methods will be used for rendering the attractor. These are so inefficient as to be unsuitable for use in decompressing fractally coded images. The authors introduce a deterministic algorithm, minimum point plotting (MPP), which is optimal in the number of pixels plotted on a graphics screen without requiring an auxiliary frame store. Its efficiency in rendering simple test fractals on a sequential computer is compared to the Monte Carlo method. A generalization of the algorithm, called the Generation Game (G/sup 2/), is readily shown to be a variant of the previously described image transformation algorithm (ITA), using different initial conditions. MPP is superior to ITA for sequential machines, and G/sup 2/ is at worst equivalent for parallelapplications. A further generalization of G/sup 2/ is the constant mass algorithm (CMA), which can be used to render colour and grey scale images, and comparisons of CMA with Monte Carlo methods are also given.< >
This conference proceedings contains 142 papers. The topics covered are interpretation/recognition;parallelprocessing;industrial applications;video;medical applications;segmentation and tracking;architectures;edges;f...
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This conference proceedings contains 142 papers. The topics covered are interpretation/recognition;parallelprocessing;industrial applications;video;medical applications;segmentation and tracking;architectures;edges;filtering;and enhancement/restoration
This paper describes the design and application areas of a real-time front end imageprocessing system. The system is designed to enhance the performance of any general imageprocessing system by providing real-time p...
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This paper describes the design and application areas of a real-time front end imageprocessing system. The system is designed to enhance the performance of any general imageprocessing system by providing real-time pre-processing functions. The system consists of a number of hardware processing units which perform their functions in parallel. The processing units make use of versatile memory units (VMUs) instead of framestores to increase system speed and make possible various novel architectures. The processing units and VMUs are interconnected by a cross-point switching network. The system can process a 256 × 256 × 8 bit image at 50Hz. The output is standard monochrome CCIR video which can be sent directly to an imageprocessing system.
The computational overheads associated with the evaluation of a discriminant function in many classification tasks may be considerable in practice and for maximum efficiency it is desirable to seek ways in which to re...
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The computational overheads associated with the evaluation of a discriminant function in many classification tasks may be considerable in practice and for maximum efficiency it is desirable to seek ways in which to reduce the computational demands. A satisfactory approach, appropriate where a potentially very powerful computational infrastructure is available, is to define a more efficient architecture which is better matched to the implementational base. This paper will consider these issues with respect to a particular type of classifier architecture and investigate and assess experimentally the relationship between the internal structure of the classifier and the implementational infrastructure realised in terms of transputer array.
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