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检索条件"任意字段=IEE Colloquium on Parallel Architectures for Image Processing Applications"

共 165 条记录，以下是61-70 订阅

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Top-down structured parallelisation of embedded image and vision applications

Top-down structured parallelisation of embedded image and vi...

引用

iee colloquium on parallel architectures for image processing

作者： A.C. Downton R.W.S. Tregidgo A. Cuhadar Department of Electronic Systems Engineering University of Essex Colchester UK Dept. of Electron. Syst. Eng. Essex Univ. Colchester UK

The authors propose an architecture-independent structured top-down design methodology for parallel embedded systems. This methodology proceeds from the observation that embedded signal processing systems may be characterized as consisting of series of independent processing stages. The methodology proposes mapping this sequential software structure to a generalized parallel architecture for embedded systems based upon a pipeline of stages with well-defined data communication patterns between them. Each stage of the pipeline then exploits parallelism in the most appropriate way, for example data parallelism applied at various different levels, algorithmic parallelism, or temporal multiplexing of complete input data sets. Processor farming, which is easily adapted to all of these models of parallelism, has been proposed as a general implementation method, because it allows indefinite incremental scaling of any stage and results in a single tractable analytical model.< >

关键词： Machine vision image processing parallel architectures

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A programmable-logic based multiprocessor engine for real-time vision preprocessing

A programmable-logic based multiprocessor engine for real-ti...

引用

iee colloquium on High Performance applications of parallel architectures

作者： S. Freeman L. Spacek V. Callaghan P. Chernett University of Essex Colchester UK Essex Univ. Colchester UK

Real-time vision is central to many embedded applications (e.g. vehicle guidance). It is a computationally intensive task well beyond current general purpose computing platforms such as PCs and workstations. Thus, most real time vision systems need special high performance computing platforms, commonly provided in the form of parallel processing engines or dedicated hardware. The proposed architecture uses new generations of re-programmable logic devices and modularised hardware, thereby gaining the performance advantage of hard-wired logic with the flexibility and associated economies of programmable systems. The architecture takes the form of an extensive processing hierarchy consisting of a set of tightly coupled parallel processors, each processing a portion of the image using a classic pipeline arrangement. A programmable image splitting (and reconstruction) engine feeds this array and offers the potential of further enhancing the performance of the engines by restructuring the pixel distribution (bit-shuffling) so as to match the requirements of the executing algorithms. The physical implementation will be based on a modularised bus system together with EPLD processing devices. The authors report on the predicted performance of low level vision functions running on this architecture.< >

关键词： Machine vision image processing Logic arrays Multiprocessing parallel architectures Real time systems

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Novel approaches to parallel volume rendering

Novel approaches to parallel volume rendering

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iee colloquium on parallel architectures for image processing

作者： P.M. Wright P.R. Croll P. Hall Department Information Studies University of Sheffield Sheffield UK Department of Computer Science University of Sheffield Sheffield UK Department of Computer Science Victoria University of Wellington Wellington New Zealand

Visible volume rendering is a computer graphics technique allowing researchers to view complex scientific data in a new, and previously impossible manner. The main problem with this technique however, is the excessive time taken to produce images from all but the simplest of data sets. What is proposed in this article is a novel volume rendering technique, utilising parallel architecture in order to reduce processing times, whilst preserving high image quality.< >

关键词： image processing parallel architectures

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High performance classification of image data through the parallel realisation of pyramidal processing structures

High performance classification of image data through the pa...

引用

iee colloquium on parallel architectures for image processing

作者： C.C. Allgrove K.D. Cowley M.C. Fairhurst Electron. Eng. Labs. Kent Univ. UK Electronic Engineering Laboratories University of Kent Canterbury Kent UK

This paper addresses a number of important issues related to the specification and implementation of high performance algorithms for pattern classification. In particular, performance is optimised by efficient implementation using a parallel processing computational infrastructure and the specification of techniques which allow the opportunity for an effective pattern rejection mechanism and a means for decision making at the earliest stage in the processing chain consistent with avoiding degradation of recognition performance. The techniques proposed are general purpose and may be applied to hierarchical pyramidal structures of any order.< >

关键词： parallel algorithms Pattern recognition

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SPARC-GAP: a parallel genetic algorithm processing platform

SPARC-GAP: a parallel genetic algorithm processing platform

引用

iee colloquium on High Performance applications of parallel architectures

作者： T.A. York D. Patrick J. Stinchcombe M.S. Szolkowski S.G. Tyrell P.R. Green Department of Electrical Engineering and Electronics University of Manchester Institute of Science and Technology Manchester UK

Genetic algorithms (GA) have emerged as a powerful technique for solving NP-complete problems, most notably those requiring optimisation of a system within a given set of constraints. The authors propose a novel attempt to realise a relatively low-cost parallel processing platform hosted on a Sun workstation that will enable unimpeded exploration of genetic algorithms. The system will be implemented on the SPARC-GAP platform.< >

关键词： Genetic algorithms parallel algorithms parallel architectures parallel machines

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parallel implementation of pyramidal classifier structures for high performance pattern recognition applications

Parallel implementation of pyramidal classifier structures f...

引用

iee colloquium on High Performance applications of parallel architectures

作者： M.C. Fairhurst K.D. Cowley Electronic Engineering Laboratories University of Kent Canterbury Kent UK

The authors address a number of important issues related to the specification and implementation of high performance algorithms for pattern classification. In particular, performance is optimised by efficient implementation using a parallel processing computational infrastructure and the specification of techniques which allow the opportunity for an effective pattern rejection mechanism and a means for decision making at the earliest stage in the processing chain consistent with avoiding degradation of recognition performance. The techniques proposed are general purpose and may be applied to hierarchical pyramidal structures of any order.< >

关键词： parallel algorithms Pattern recognition

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Mapping image processing algorithms onto abstract multiprocessors

Mapping image processing algorithms onto abstract multiproce...

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iee colloquium on Mathematical Modelling and Simulation of Industrial and Economic Processes

作者： I. Erenyi Z. Fazekas KFKI Research Institute of Measurement and Computing Techniques Budapest Hungary

The need for parallel computing technology is rapidly growing in several image processing applications, such as industrial quality control, bio-medical imaging, traffic control automation. Most of the image processing algorithms are inherently computationally intensive and may require vast computing power if strict time-constraints are posed. The spreading of parallel image processing techniques and systems has been driven not only by the afore-mentioned need, but the inherent parallel nature of many image processing algorithms has also eased this evolution. The execution characteristics of a certain parallel algorithm on a given architecture heavily depends on the 'mutual conformance' of the mentioned algorithm and the architecture pair. Two algorithms with similar sequential performance may behave very differently in a parallel environment. In sequential algorithms the complexity is expressed in terms of operations and storage. In parallel environments these terms are not adequate for characterizing the computing efficiency - fewer operations does not directly mean shorter execution time since there is a definite overhead involved due to availability of resources and communication between processors.< >

关键词： image processing parallel algorithms parallel architectures

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parallel processing for real-time adaptive robot control: theoretical issues and practical implementation

Parallel processing for real-time adaptive robot control: th...

引用

iee colloquium on High Performance applications of parallel architectures

作者： S.M. Ziauddin A.M.S. Zalzala Robotics Research Group Department of Automatic Control and Systems Engineering University of Sheffield Sheffield UK

The authors present a practical solution to the problem of real-time robot control including the nonlinear dynamic model of the manipulator by employing a parallel processing approach. The parallelism inherent in the adaptive controllers is exploited to obtain an efficient implementation that reduces the overall computation time to within the limit acceptable for real-time control. The distributed algorithm is implemented on a network of transputers for the six-joint PUMA 560 arm.< >

关键词： Adaptive control Nonlinear systems parallel algorithms Real time systems Robot programming Robots

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parallel architectures for real-time control

Parallel architectures for real-time control

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iee colloquium on High Performance applications of parallel architectures

作者： M.O. Tokhi M.A. Hossain M.J. Baxter P.J. Fleming Department of Automatic Control and Systems Engineering University of Sheffield Sheffield UK

The authors present an investigation into the utilisation of parallel computing techinques for real-time simulation and control of a flexible beam structure in transverse vibration. The performance demands of modern control systems require the employment of complex algorithms with demanding operations which, in turn, leads to shorter sampling times. Therefore, real-time performance in control applications where the use of advanced control methods is warranted becomes difficult to accomplish. Many demanding complex control processes cannot be satisfactorily realised with conventional uni-processor and multi-processor systems. Previous investigations have demonstrated the limitations of employing only transputers for real-time implementations in control applications. Alternative strategies where multi-processor based systems are employed, utilising digital signal processing (DSP) and parallel processing techniques, could provide suitable methodologies.< >

关键词： Digital control Simulation parallel architectures Real time systems Signal processing Structural engineering Computer aided engineering

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A transputer-based parallel DSP environment

A transputer-based parallel DSP environment

引用

iee colloquium on High Performance applications of parallel architectures

作者： M. Razaz K.A. Marlow School of Information Systems University of East Anglia Norwich UK

The traditional DSP design and development environment is generally based on the use of a single processor and suffers from a number of limitations including the following: a time-consuming design cycle from specification to the final product development; dependence on hardware and hence lack of portability to different DSP platforms; lack of exploitation of algorithmic and architectural parallelism for DSP design. The authors present a multiprocessor environment, called Taurus, for design and development of DSP algorithms and applications. The important features of such environment are introduced, and typical experimental results using an ADPCM system are presented and discussed.< >

关键词： parallel machines parallel programming Pulse code modulation Signal processing

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