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Shedding Light on LLMs: Harnessing Photonic Neural Networks for Accelerating LLMs 24

Shedding Light on LLMs: Harnessing Photonic Neural Networks ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Afifi, Salma Pasricha, Sudeep Nikdast, Mahdi Department of Electrical and Computer Engineering Colorado State University Fort CollinsCO United States

ISBN: (纸本)9798400710773

Large language models (LLMs) are foundational to the advancement of state-of-the-art natural language processing (NLP) and computer vision applications. However, their intricate architectures and the complexity of their underlying neural networks present significant challenges for efficient acceleration on conventional electronic platforms. Silicon photonics offers a compelling alternative. In this paper, we describe our recent efforts on developing a novel hardware accelerator that leverages silicon photonics to accelerate transformer neural networks integral to LLMs. Our evaluation demonstrates that the proposed accelerator delivers up to 14× higher throughput and 8× greater energy efficiency compared to leading-edge LLM hardware accelerators, including CPUs, GPUs, and TPUs. © 2024 Copyright is held by the owner/author(s).

关键词： Silicon photonics

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Accelerating Fault Injection for Validating Processor RTL Implementations 24

Accelerating Fault Injection for Validating Processor RTL Im...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Yuan, Yi Chiou, Derek The University of Texas at Austin AustinTX United States Microsoft Corporation RedmondWA United States

ISBN: (纸本)9798400710773

With the increasing probability of software errors being caused by hardware transient faults, hardware engineers require better methods to evaluate the impact of faults and determine how to harden their products against them. This paper presents novel techniques to accurately and efficiently simulate faults on processors by dynamically switching, with little designer effort, a simulation from RTL-level-or-lower to instruction-level. When combined with known techniques, the proposed techniques make fault modeling orders-of-magnitude faster than RTL simulation while achieving the same level of accuracy, enabling fast identification of the portions of the design that would benefit most from hardening, and providing statistical guarantees of a design’s resistance to faults. © 2024 Copyright is held by the owner/author(s).

关键词： computer hardware description languages

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Proceedings of the 43rd ieee/acm international conference on computer-aided Design, ICCAD 2024

Proceedings of the 43rd IEEE/ACM International Conference on...

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43rd international conference on computer-aided Design, ICCAD 2024

ISBN: (纸本)9798400710773

The proceedings contain 239 papers. The topics discussed include: exploration of timing and higher-energy attacks on quantum random access memory;fortifying the NAND flash supply chain with innovative security primitives;optimizing supply chain management using permissioned blockchains;systematic use of random self-reducibility in cryptographic code against physical attacks;enhancing privacy-preserving computing with optimized CKKS encryption: a hardware acceleration approach;a hypergraph partitioner utilizing a novel graph generative model;TopoOrderPart: a multi-level scheduling-driven partitioning framework for processor-based emulation;modern fixed-outline floorplanning with rectilinear soft modules;JigsawPlanner: jigsaw-like floorplanner for eliminating whitespace and overlap among complex rectilinear modules;and an effective analytical placement approach to handle fence region constraint.

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Detecting Hardware Trojans in Manufactured Chips without Reference: A GMM-Based Approach 24

Detecting Hardware Trojans in Manufactured Chips without Ref...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Tahghigh, Mahsa Salmani, Hassan Howard University WashingtonDC United States

ISBN: (纸本)9798400710773

The horizontal IC design and manufacturing flow creates ample opportunities for unauthorized tampering at various stages, yet there is limited research dedicated to detecting hardware Trojans (HTs) in manufactured ICs. Practical applications are hindered by substantial challenges, including the presence of trusted ICs. This paper introduces a novel method for reference-free HT detection in manufactured ICs, leveraging Gaussian mixture models (GMMs) with power side-channel signals. Experimental results, conducted on AES-128 with various hardware Trojans, demonstrate an accuracy exceeding 95.52%. To be introduced for the first time, to the best of our knowledge, our proposed GMM-based HT detection method also provides a probabilistic framework, attributing evolving probability values to individual side-channel measurements to indicate potential HT activation. Consequently, it becomes feasible to ascertain with a high level of confidence whether a manufactured design has been tampered with an HT. © 2024 Copyright is held by the owner/author(s).

关键词： computer viruses

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MapFormer: Attention-based multi-DNN Manager for Throughout & Power Co-Optimization on Embedded Devices 24

MapFormer: Attention-based multi-DNN Manager for Throughout ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Karatzas, Andreas Anagnostopoulos, Iraklis School of Electrical Computer and Biomedical Engineering Southern Illinois University Carbondale United States

ISBN: (纸本)9798400710773

In the context of modern services that use multiple Deep Neural Networks (DNNs), managing workloads on embedded devices presents unique challenges. These devices often incorporate diverse architectures, necessitating advanced management solutions to efficiently deploy multi-DNN workloads. Traditionally, the focus has been on improving throughput, while power optimization has received less attention. This paper presents MapFormer, a new manager that uses attention-based mechanisms to enhance both throughput and power efficiency. MapFormer intelligently assigns multi-DNN workloads to different computing components of embedded systems—CPU, GPU, and DLA—and adjusts operational frequencies to optimize power use. Experimental results show that MapFormer significantly improves average throughput under set power budgets by 90.8%, offering a promising approach for managing complex workloads on heterogeneous embedded systems. © 2024 Copyright is held by the owner/author(s).

关键词： Budget control

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ALISA: An Adaptive Learned Index Structure for Spatial Data on Solid-State Drives 24

ALISA: An Adaptive Learned Index Structure for Spatial Data ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Lin, Che-Wei Wu, Chun-Feng Department of Computer Science National Yang Ming Chiao Tung University Taiwan

ISBN: (纸本)9798400710773

Spatial learned index is becoming popular as a solution to relieve the intense storage demands and high I/O costs of spatial databases. LISA, the original and most prominent spatial learned index structure, is tailored for HDD-resident spatial data and comes with strict data arrangement requirements. Given that direct SSD migration may drastically impair SSD durability especially when page utilization is low, this work aims to adapt this innovative index structure to SSDs to leverage the faster performance and expand application possibilities. We propose an Adaptive Learned Index structure for Spatial dAta on SSDs (ALISA), with mechanisms to persistently monitor updated data distribution and adaptively restructure to align with SSD access characteristics. The evaluation results show that ALISA can significantly extend SSD lifespan and improve low page utilization, thereby enhancing query performance. © 2024 Copyright is held by the owner/author(s).

关键词： Dynamic random access storage

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Invited Paper: Enhancing Privacy-Preserving Computing with Optimized CKKS Encryption: A Hardware Acceleration Approach 24

Invited Paper: Enhancing Privacy-Preserving Computing with O...

引用

43rd international conference on computer-aided Design, ICCAD 2024

作者： Bao, Tianyou He, Pengzhou Xie, Jiafeng Department of Electrical and Computer Engineering Villanova University VillanovaPA19085 United States

ISBN: (纸本)9798400710773

The widespread adoption of the FHE (Fully Homomorphic Encryption) CKKS (Cheon-Kim-Kim-Song) encryption algorithm is stunted by its slow software implementation, driving the need for efficient hardware acceleration solutions. This paper presents a novel approach to address the challenge by optimizing a segment of the CKKS encryption and decryption process. Using the Residue Number System (RNS), the inputs are encoded into 32-bit representations and processed through the number theoretic transform (NTT). This innovative strategy reduces the utilities of the hardware resources and also accelerates calculations. This unified calculation methodology is designed to adapt inputs of diverse bit widths, seamlessly decoding them back into their original format after the CRT calculation, thereby significantly enhancing the throughput of calculations. We hope this work advances privacy-preserving computing in resource-constrained environments. © 2024 Copyright is held by the owner/author(s).

关键词： Number theory

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RareLS: Rarity-Reducing Logic Synthesis for Mitigating Hardware Trojan Threats 24

RareLS: Rarity-Reducing Logic Synthesis for Mitigating Hardw...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Meng, Chang Yu, Mingfei Wang, Hanyu Burleson, Wayne De Micheli, Giovanni EPFL Lausanne Switzerland ETH Zurich Zurich Switzerland University of Massachusetts Amherst United States

ISBN: (纸本)9798400710773

Hardware Trojan (HT) poses a critical security threat to integrated circuits, which can change circuit functionality or leak sensitive data. HTs are typically activated under low-probability conditions by exploiting "rare signals" in logic circuits. In this paper, we propose RareLS, rarity-reducing logic synthesis for mitigating HT threats. Specifically, RareLS reduces the number of rare signals through rarity-oriented technology-independent optimization and technology mapping. Experimental results show that RareLS reduces rare signals by 63.4% on average, with a small overhead of 4.0% in area, 1.9% in delay, and 6.2% in power. Moreover, RareLS complicates HT insertion for attackers by reducing HT trigger logic by 92.94%, and aids defenders in detecting HTs by shortening the test length by more than 80.83%. © 2024 Copyright is held by the owner/author(s).

关键词： computer viruses

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SMT-based Layout Synthesis for Silicon-based Quantum Computing with Crossbar Architecture 24

SMT-based Layout Synthesis for Silicon-based Quantum Computi...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Huang, Sheng-Tan Jiang, Ying-Jie Fang, Shao-Yun Cheng, Chung-Kuan Department of Electrical Engineering National Taiwan University of Science and Technology Taiwan Department of Computer Science and Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

With the announcement of the most advanced silicon spin quantum-bit (qubit) chip by Intel, silicon-based quantum circuit manufacturing technology has shown the superior potential to realize quantum computing to other technologies because of the mature semiconductor manufacturing technologies and the compatibility with electronics. Due to the bottleneck in scalability caused by interconnections in silicon-based quantum circuits, crossbar architectures serve as one of the most promising solutions for circuitry implementation. This paper proposes the first satisfiability modulo theories (SMT) formulation to optimally solve the layout synthesis problem by simultaneously performing scheduling, mapping, and routing for silicon-based quantum systems with a specific crossbar architecture. The experiments demonstrate that the proposed method can effectively generate layout synthesis results with minimal usage of swap and shuttle gates within the shortest circuit depths, and the solutions greatly outperform those derived from a state-of-the-art work. © 2024 Copyright is held by the owner/author(s).

关键词： Qubits

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Hardware-Aware Quantization for Accurate Memristor-Based Neural Networks 24

Hardware-Aware Quantization for Accurate Memristor-Based Neu...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Diware, Sumit Yaldagard, Mohammad Amin Bishnoi, Rajendra Computer Engineering Lab Delft University of Technology Delft Netherlands

ISBN: (纸本)9798400710773

Memristor-based Computation-In-Memory (CIM) has emerged as a compelling paradigm for designing energy-efficient neural network hardware. However, memristors suffer from conductance variation issue, which introduces computational errors in CIM hardware and leads to a degraded inference accuracy. In this paper, we present a hardware-aware quantization to mitigate the impact of conductance variation on CIM-based neural networks. We achieve this using the inherent characteristics of fixed-point arithmetic in CIM hardware. By tuning the bit-precision of weights, we align the conductance variation-induced errors with lower-order output bits. This reduces their numerical impact on the fixed-point output. We further decrease the residual errors by selectively discarding bits with low information and high error. This leads to error-free computations and a high inference accuracy. Our proposed methodology achieves 5.6× correct operations per unit energy compared to the conventional approach, while incurring very low hardware overheads. © 2024 Copyright is held by the owner/author(s).

关键词： Fixed point arithmetic

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