This paper studies the effects of clustering as a pre-processing step and routability estimation in the placement flow. The study shows that when clustering and routability estimation are considered, the placer effect...
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ISBN:
(纸本)9781605588001
This paper studies the effects of clustering as a pre-processing step and routability estimation in the placement flow. The study shows that when clustering and routability estimation are considered, the placer effectively improves the routed wirelength for the circuits of IBM-PLACE 2.0 standard-cell Benchmark Suite [1] and results in the best average routed wirelength when compared against state-of-the-art academic placers. Copyright 2009 acm.
The term resilience is used differently by different communities. In general engineering systems, fast recovery from a degraded system state is often termed as resilience. computer networking community defines it as t...
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ISBN:
(纸本)9781605588001
The term resilience is used differently by different communities. In general engineering systems, fast recovery from a degraded system state is often termed as resilience. computer networking community defines it as the combination of trustworthiness (dependability, security, performability) and tolerance (survivability, disruption tolerance, and traffic tolerance). Dependable computing community defined resilience as the persistence of service delivery that can justifiably be trusted, when facing changes. In this paper, resilience definitions of systems and networks will be presented. Metrics for resilience will be compared with dependability metrics such as availability, performance, performability. Simple examples will be used to show quantification of resilience via probabilistic analytic models. Copyright 2009 acm.
In this paper we propose a methodology for energy efficient Spin-Torque-Transfer Random Access Memory (STTRAM) array design at scaled technology nodes. We present a model to estimate and analyze the energy dissipation...
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ISBN:
(纸本)9781605588001
In this paper we propose a methodology for energy efficient Spin-Torque-Transfer Random Access Memory (STTRAM) array design at scaled technology nodes. We present a model to estimate and analyze the energy dissipation of an STTRAM array. The presented model shows the strong dependence of the array energy on the silicon transistor width, word line voltage and row/column organization. Using the array energy model we propose a design methodology for STTRAM arrays which minimizes the energy dissipation while maintaining the required robustness in read and write operations at scaled technologies. Copyright 2009 acm.
In this paper a precise formulation of the problem of minimizing the maximum completion time of tasks on a multicore processor, subject to thermal constraints is presented. The power model used in this work, accounts ...
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ISBN:
(纸本)9781605588001
In this paper a precise formulation of the problem of minimizing the maximum completion time of tasks on a multicore processor, subject to thermal constraints is presented. The power model used in this work, accounts for the leakage dependence on temperature, while the thermal model is based on the HotSpot model. The general problem is shown to be a non-linear optimization problem that includes cyclic constraints between temperature and power. The derived policy of dynamic frequency and voltage control results in a performance improvement of 19.6% over an optimal policy which performs speed-only *** 2009 acm.
As SOC designs are getting more popular, the importance of design automation for analog and mixed-signal ICs is increasing. In this paper, we study the problem of exact route matching, which is an important physical d...
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ISBN:
(纸本)9781605588001
As SOC designs are getting more popular, the importance of design automation for analog and mixed-signal ICs is increasing. In this paper, we study the problem of exact route matching, which is an important physical design constraint commonly imposed on specific analog signals for the purpose of correct analog functionality. For this, we first propose a mathematical formulation that models the route matching problem exactly. Based on this formulation, we derive important theoretical conclusions, and propose dynamic-programming algorithms to solve the problem. We also discuss how to use heuristic search techniques to enable faster computations. Our experimental results show the effectiveness of our algorithms. Copyright 2009 acm.
In this paper, we propose a new node merging algorithm using logic implications. The proposed algorithm only requires two logic implications to find the substitute nodes for a given target node, and thus can efficient...
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ISBN:
(纸本)9781605588001
In this paper, we propose a new node merging algorithm using logic implications. The proposed algorithm only requires two logic implications to find the substitute nodes for a given target node, and thus can efficiently detect node mergers. Furthermore, we also apply the node merger identification algorithm for area optimization in VLSI circuits. We conduct experiments on a set of IWLS 2005 benchmarks. The experimental results show that our algorithm has a competitive capability on area optimization compared to a global observability don't care (ODC)-based node merging algorithm which is highly time-consuming. Our speedup is approximately 86 times for overall benchmarks. Copyright 2009 acm.
Electronic design automation (EDA) tools have facilitated the design of ever more complex integrated circuits each year. Synthetic biology would also benefit from the development of genetic design automation (GDA) too...
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ISBN:
(纸本)9781605588001
Electronic design automation (EDA) tools have facilitated the design of ever more complex integrated circuits each year. Synthetic biology would also benefit from the development of genetic design automation (GDA) tools. Existing GDA tools require biologists to design genetic circuits at the molecular level, roughly equivalent to designing electronic circuits at the layout level. Analysis of these circuits is also performed at this very low level. This paper presents the background and issues involved in the development of such a GDA tool for modeling, analysis, and design. Copyright 2009 acm.
In this paper, we present an efficient method to solve the obstacle-avoiding rectilinear Steiner tree problem optimally. Our work is developed based on the GeoSteiner approach, modified and extended to allow rectiline...
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ISBN:
(纸本)9781605588001
In this paper, we present an efficient method to solve the obstacle-avoiding rectilinear Steiner tree problem optimally. Our work is developed based on the GeoSteiner approach, modified and extended to allow rectilinear blockages in the routing region. We extended the proofs on the possible topologies of full Steiner tree (FST) in [4] to allow blockages, where FST is the basic concept used in GeoSteiner. We can now handle hundreds of pins with multiple blockages, generating an optimal solution in a reasonable amount of time. This work serves as a pioneer in providing an optimal solution to this difficult problem. Copyright 2009 acm.
Escape routing is a critical problem in PCB design. In ICCAD'07, a layer assignment algorithm was proposed for escape routing of buses. The algorithm is optimal for single layer design in the sense that it determi...
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ISBN:
(纸本)9781605588001
Escape routing is a critical problem in PCB design. In ICCAD'07, a layer assignment algorithm was proposed for escape routing of buses. The algorithm is optimal for single layer design in the sense that it determines if a set of buses can all be escaped on one layer. If they cannot, the algorithm is able to select a maximum subset of the buses that can be escaped on one layer. This, in turn, leads to a heuristic for the layer assignment problem with multiple layers, which is to repeatedly assign a maximum subset of the unassigned buses to a new layer. In this work, we present an algorithm that solves the multi-layer layer assignment problem optimally. Our algorithm guarantees to produce a layer assignment with minimum number of layers. We applied our algorithm on industrial data and obtained encouraging results. Copyright 2009 acm.
Recent progress in the area of global routing has been remarkable;yet, in many ways, the classical formulation has yet to catch up with the demands imposed by modern physical synthesis flows. In this work, we visit (a...
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ISBN:
(纸本)9781605588001
Recent progress in the area of global routing has been remarkable;yet, in many ways, the classical formulation has yet to catch up with the demands imposed by modern physical synthesis flows. In this work, we visit (and revisit) the topic of global routing. We provide a brief review of global routing's history, and touch on recent work that has contributed to the state-of-the-art in the field. While we cover in depth the basic principles behind leading approaches, we also emphasize open challenges and problems that remain unresolved. We argue that not only does the current academic formulation lack key components of the true routing problem - such as scenic control, layer directives, and capabilities for integration with physical synthesis - but also that present methods are likely to fail when extended toward the more generalized formulation. Finally, we offer a revised incarnation of the ISPD benchmarks to encourage continued progress in the research community. Copyright 2009 acm.
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