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Introduction to GPU programming for EDA 09

Introduction to GPU programming for EDA

引用

2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Croix, John F. Khatri, Sunil P. Cadence Design Systems San Jose CA 95134 United States Department of Electrical and Computer Engineering Texas A and M University College Station TX 77843 United States

ISBN: (纸本)9781605588001

Advances in GPU technology have propelled the GPU into arenas far afield from the traditional, isolated roles they have previously played. With hundreds of processing units in a single GPU, substantial speedups can be achieved by harnessing their power to augment the performance of the traditional single- or multi-core CPU on certain compute-intensive applications. However, utilizing the GPU requires both a change in the programmer's traditional algorithmic model as well as a judicious selection of algorithm being used for the problem. This paper reviews the GPU architecture and the tools available to utilize this valuable resource. It also provides insight into the type of problem best suited for the GPU as well as programming styles required to fully harness the power of the GPU. We present examples of specific EDA algorithms that can benefit from GPU acceleration, using both the CUDA and OpenCL environments. Copyright 2009 acm.

关键词： Graphics processing unit

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Energy reduction for STT-RAM using early write termination 09

Energy reduction for STT-RAM using early write termination

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2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Zhou, Ping Zhao, Bo Yang, Jun Zhang, Youtao Electrical and Computer Engineering Department Department of Computer Science University of Pittsburgh Pittsburgh PA 15261 United States

ISBN: (纸本)9781605588001

The emerging Spin Torque Transfer memory (STT-RAM) is a promising candidate for future on-chip caches due to STT-RAM's high density, low leakage, long endurance and high access speed. However, one of the major challenges of STT-RAM is its high write current, which is disadvantageous when used as an on-chip cache since the dynamic power generated is too high. In this paper, we propose Early Write Termination (EWT), a novel technique to signifcantly reduce write energy with no performance penalty. EWT can be implemented with low complexity and low energy overhead. Our evaluation shows that up to 80% of write energy reduction can be achieved through EWT, resulting 33% less total energy consumption, and 34% reduction in ED2. These results indicate that EWT is an effective and practical scheme to improve the energy efficiency of a STT-RAM cache. Copyright 2009 acm.

关键词： Energy utilization

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Pad assignment for die-stacking system-in-package design 09

Pad assignment for die-stacking system-in-package design

引用

2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Lin, Yu-Chen Mak, Wai-Kei Chu, Chris Wang, Ting-Chi Department of Computer Science National Tsing Hua University Hsinchu 300 Taiwan Department of Electrical and Computer Engineering Iowa State University Ames IA 50011 United States

ISBN: (纸本)9781605588001

Wire bonding is the most popular method to connect signals between dies in System-in-Package (SiP) design nowadays. Pad assignment, which assigns inter-die signals to die pads so as to facilitate wire bonding, is an important physical design problem for SiP design because the quality of a pad assignment solution *** both the cost and performance of a SiP design. In this paper, we study a pad assignment problem, which prohibits the generation of illegal crossings and aims to minimize the total signal wirelength, for die-stacking SiP design. We first consider a variety of special cases and present a minimum-cost maximum-.ow based approach to optimally solve them in polynomial time. We then describe an approach, which uses a *** left edge algorithm and an integer linear programming technique, to solve the general case. Encouraging experimental results are shown to support our approaches. Copyright 2009 acm.

关键词： System-in-package

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Intrinsic NBTI-variability aware statistical pipeline performance assessment and tuning 09

Intrinsic NBTI-variability aware statistical pipeline perfor...

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2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Vaidyanathan, Balaji Oates, Anthony S. Xie, Yuan Department of Computer Science and Engineering Pennsylvania State University Pennsylvania PA 16801 United States Technology Reliability Physics Dept. R and D Taiwan Semiconductor Manufacturing Company Hsinchu Taiwan

ISBN: (纸本)9781605588001

Random process variation and variability intrinsic to PMOS Negative Bias Temperature Instability (NBTI-induced statistical variation) are two major reliability concerns as transistor dimensions scales with technology. Previous works have studied these two sources of variation separately at device and circuit level. We study the impact of the interaction between intrinsic PMOS NBTI variability and time0 process variability on circuit delay spread. A statistical pipeline timing error model is proposed including both the variability sources to predict its impact on pipeline stage count. It is shown that a wide difference in statistical timing response to intrinsic NBTI variability exists among different circuits. Traditional design time NBTI-aware delay guard-banding is proved to be statistically insufficient in pipelines and an excess of 2x guard-band needs to be incorporated at the end of 10 years. However, the guard-band is shown to be reduced by 30% when the dynamic cycle time stealing technique is employed. Copyright 2009 acm.

关键词： Negative bias temperature instability

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Synthesizing complementary circuits automatically 09

Synthesizing complementary circuits automatically

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2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Shen, ShengYu Zhang, JianMin Qin, Ying Li, SiKun School of Computer Science National University of Defense Technology 410073DeYa Avenue Changsha China

ISBN: (纸本)9781605588001

One of the most difficult jobs in designing communication and multimedia chips, is to design and verify complex complementary circuit pair (E,E -1), in which circuit E transforms information into a format that is suitable for transmission and storage, while E's complementary circuit E -1 recovers this information. In order to ease this job, we propose a novel two-step approach to synthesize complementary circuit E-1 from E fully automatically. First, we assume that the circuit E satisfies parameterized complementary assumption, which means its input can be recovered from its output under some parameter setting. We check this assumption with SAT solver and find out proper values of these parameters. Second, with parameter values and the SAT instance obtained in the first step, we build the complementary circuit E-1 with an efficient satisfying assignments enumeration technique that is specially designed for circuits with lots of XOR gates. To illustrate its usefulness and efficiency, we run our algorithm on several complex encoders from industrial projects, including PCIE and 10G ethernet, and successfully generate correct complementary circuits for them. Copyright 2009 acm.

关键词： Timing circuits

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Timing arc based logic analysis for false noise reduction 09

Timing arc based logic analysis for false noise reduction

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2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Palla, Murthy Bargfrede, Jens Eggersglüß, Stephan Anheier, Walter Drechsler, Rolf ITEM University of Bremen Bremen Germany Infineon Technologies AG Munich Germany Institute of Computer Science University of Bremen Bremen Germany

ISBN: (纸本)9781605588001

The problem of calculating accurate impact of crosstalk on a circuit considering its inherent logic and timing properties is very complex. Although it has been widely studied, it still lacks an efficient solution. As a result, state-of-the-art crosstalk calculators use simplistic and overly pessimistic models resulting in the overestimation of crosstalk effects. Such pessimism in crosstalk analysis often leads to the triggering of false violations and consequently an inefficient use of design resources. The main contribution of this paper is a novel technique called Timing Arc Based Logic Analysis (TABLA) that serves as an efficient means to calculate realistic crosstalk bounds. TABLA uses timing arcs as basic elements to perform an efficient temporal logic analysis employing the min-max timing model using dedicated solvers for logic and timing. Additionally, a procedure to generate powerful conflict clauses is proposed to improve the run time of the overall analysis. The proposed technique has been tested in an industrial environment on benchmark circuits as well as on an industrial design, and results are provided. Copyright 2009 acm.

关键词： Crosstalk

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How to consider shorts and guarantee yield rate improvement for redundant wire insertion 09

How to consider shorts and guarantee yield rate improvement ...

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2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Chang, Fong-Yuan Tsay, Ren-Song Mak, Wai-Kei Department of Computer Science National Tsing-Hua University Hsinchu Taiwan Springsoft Inc. Taiwan

ISBN: (纸本)9781605588001

This paper accurately considers wire short defects and proposes an algorithm to guarantee IC chip yield rate improvement for redundant wire insertion. Without considering yield rate degradation caused by shorts, traditional methods may even lead to yield rate loss. However, shorts are more complicated to analyze than opens. Moreover, since any two points of a routed net can be connected by a redundant wire, the number of possible insertion patterns for a chip is un-tractable. To maximize yield rate improvement and to make the problem tractable, we identify a key insight, tolerance-ratio, as an effective guide for choosing insertion patterns and insertion order. Finally, to guarantee yield rate improvement , only positive gain redundant wires are committed. Experimental results show that, compared with unprocessed cases, all yield rate improvements in the proposed algorithm are positive, and the defect rates are reduced by up to 65% and by 24% on average. On the other hand, without considering shorts, the defect rate can increase as much as 7%. Copyright 2009 acm.

关键词： Wire

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The synthesis of combinational logic to generate probabilities 09

The synthesis of combinational logic to generate probabiliti...

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2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Qian, Weikang Riedel, Marc D. Bazargan, Kia Lilja, David J. Department of Electrical and Computer Engineering University of Minnesota Twin Cities MN United States

ISBN: (纸本)9781605588001

As CMOS devices are scaled down into the nanometer regime, concerns about reliability are mounting. Instead of viewing nanoscale characteristics as an impediment, technologies such as PCMOS exploit them as a source of randomness. The technology generates random numbers that are used in probabilistic algorithms. With the PCMOS approach, different voltage levels are used to generate different probability values. If many different probability values are required, this approach becomes prohibitively expensive. In this work, we demonstrate a novel technique for synthesizing logic that generates new probabilities from a given set of probabilities. Three different scenarios are considered in terms of whether the given probabilities can be duplicated and whether there is freedom to choose them. In the case that the given probabilities cannot be duplicated and are predetermined, we provide a solution that is FPGA-mappable. In the case that the given probabilities cannot be duplicated but can be freely chosen, we provide an optimal choice. In the case that the given probabilities can be duplicated and can be freely chosen, we demonstrate how to generate arbitrary decimal probabilities from small sets - a single probability or a pair of probabilities - through combinational logic. Copyright 2009 acm.

关键词： Probability

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Pre-ATPG path selection for near optimal post-ATPG process space coverage 09

Pre-ATPG path selection for near optimal post-ATPG process s...

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2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Xiong, Jinjun Shi, Yiyu Zolotov, Vladimir Visweswariah, Chandu IBM Research Center Yorktown Heights NY 10598 United States IBM System and Technology Hopewell Junction NY 12533 United States EE Dept UCLA Los Angeles CA 90095 United States

ISBN: (纸本)9781605588001

Path delay testing is becoming increasingly important for high-performance chip testing in the presence of process variation. To guarantee full process space coverage, the ensemble of critical paths of all chips irrespective of their manufacturing process conditions needs to be tested, as different chips may have different critical paths. Existing coveragebased path selection techniques, however, suffer from the loss of coverage after ATPG (automatic test pattern generation), i.e., although the pre-ATPG path selection achieves good coverage, after ATPG, the coverage can be severely reduced as many paths turn out to be unsensitizable. This paper presents a novel path selection algorithm that, without running ATPG, selects a set of n paths to achieve near optimal post-ATPG coverage. Details of the algorithm and its optimality conditions are discussed. Experimental results show that, compared to the state-of-the-art, the proposed algorithm achieves not only superior post-ATPG coverage, but also significant runtime speedup. Copyright 2009 acm.

关键词： computer aided design

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Thermal modeling for 3D-ICs with integrated microchannel cooling 09

Thermal modeling for 3D-ICs with integrated microchannel coo...

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2009 ieee/acm international conference on computer-aided Design, ICCAD 2009

作者： Mizunuma, Hitoshi Yang, Chia-Lin Lu, Yi-Chang Department of Computer Science and Information Engineering National Taiwan University China Graduate Institute of Electronics Engineering Department of Electrical Engineering National Taiwan University China

ISBN: (纸本)9781605588001

Integrated microchannel liquid-cooling technology is envisioned as a viable solution to alleviate an increasing thermal stress imposed by 3D stacked ICs. Thermal modeling for microchannel cooling is challenging due to its complicated thermal-wake effect, a localized temperature wake phenomenon downstream of a heated source in the flow. This paper presents a fast and accurate thermal-wake aware thermal model for integrated microchannel 3D ICs. Validation results show the proposed thermal model achieves more than 400x speed up and only 2.0% error in comparison with a commercial numerical simulation tool. We also demonstrate the use of the proposed thermal model for thermal optimization during the IC placement stage. We find that due to the thermal-wake effect, tiles are placed in the descending order of power magnitude along the flow direction. We also find that modeling thermal-wakes is critical for generating a thermal-aware placement for integrated microchannel-cooled 3D IC. It could result in up to 25°C peak temperature difference according to our experiments. Copyright 2009 acm.

关键词： Microchannels

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