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On soft error rate analysis of scaled CMOS designs — A statistical perspective 09

On soft error rate analysis of scaled CMOS designs — A stat...

引用

ieee international conference on computer-aided Design

作者： Huan-Kai Peng Charles H.-P. Wen Jayanta Bhadra Department of Electrical and Computer Engineering Naval Aeronautical and Astronautical University Hsinchu Taiwan Freescale Semiconductor Inc. Austin TX USA

ISBN: (纸本)9781605588001

This paper re-examines the soft error effect caused by cosmic radiation in sub 90 nm technologies. Considering the impact of process variation, a number of statistical natures of transient faults are found more sophisticated than their static ones. We apply the state-of-the-art statistical learning algorithm to tackle the complexity of these natures and build compact yet accurate generation and propagation models for transient fault distributions. A statistical analysis framework for soft error rate (SER) is also proposed on the basis of these models. Experimental results show that the proposed framework can obtain improved SER estimation compared to the static approaches.

关键词： Error analysis Circuit faults SPICE CMOS technology Timing CMOS logic circuits Clocks Transient analysis Permission Circuit simulation

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From 2D to 3D NoCs: A case study on worst-case communication performance 09

From 2D to 3D NoCs: A case study on worst-case communication...

引用

ieee international conference on computer-aided Design

作者： Yue Qian Zhonghai Lu Wenhua Dou School of Computer Science National University of Defense Technology China Department of Electronic Computer and Software Systems Royal Institute of Technology Sweden

ISBN: (纸本)9781605588001

Advanced integration technologies enable the construction of Network-on-Chip (NoC) from two dimensions to three dimensions. Studies have shown that 3D NoCs can improve average communication performance because of the possibility of using the additional dimension to shorten communication distance. In this paper, we present a detailed case study on worst-case communication performance in regular k-ary-2-mesh networks. Through both analysis and simulation, we show that, while 3D networks achieve better average performance, this may not be the case for worst-case performance mainly due to constraints on vertical channels. Our analysis is based on network calculus, which allows to calculate theoretical delay bounds for constrained flows traversing network elements.

关键词： Network-on-a-chip Three-dimensional integrated circuits Integrated circuit technology Integrated circuit interconnections Scalability Performance analysis Delay Calculus Permission computer science

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GRPlacer: Improving routability and wire-length of global routing with circuit replacement 09

GRPlacer: Improving routability and wire-length of global ro...

引用

ieee international conference on computer-aided Design

作者： Ke-Ren Dai Chien-Hung Lu Yih-Lang Li Department of Computer Science National Chiao Tung University Taiwan SpringSoft Inc. Taiwan

ISBN: (纸本)9781605588001

Placement profoundly impacts physical design owing to its role in determining the lower bound of a circuit wirelength, as well as the circuit routability. To close the gap between placement and routing, this study integrates global routing and placement to improve the wirelength estimation accuracy of placement. Two methods, called wirelength-reduced cell shifting and cell rearrangement by bipartite matching, are applied to minimize wirelength. Cell sorting based congestion reduction and pattern-prerouting based congestion-avoided cell shifting are proposed to reduce congestion. Experimental results demonstrate that the proposed placer improves total routed wirelength by 2% to ROOSTER on IBMv2 benchmarks. Moreover, the proposed GRPlacer resolves the original congested regions of the placements generated by ROOSTER. Compare with the detailed placer in ROOSTER, our work can reduce more routed wire length and remove more overflows.

关键词： Routing Circuits Minimization computer science Sorting Wire White spaces Very large scale integration Delay Pins

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Iterative layering: Optimizing arithmetic circuits by structuring the information flow 09

Iterative layering: Optimizing arithmetic circuits by struct...

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ieee international conference on computer-aided Design

作者： Ajay K. Verma Philip Brisk Paolo Ienne School of Computer and Communication Sciences Ecole Polytechnique Fédérale de Lausanne Lausanne Switzerland Department of Computer Science and Engineering University of California Riverside CA USA

ISBN: (纸本)9781605588001

Current logic synthesis techniques are ineffective for arithmetic circuits. They perform poorly for XOR-dominated circuits, and those with a high fan-in dependency between inputs and outputs. Many optimizers, therefore employ libraries of hand-optimized arithmetic components, but cannot optimize across component boundaries. To remedy this situation, we introduce a new logic synthesis algorithm which analyzes the input circuit based on its behavior on a set of random assignments of input variables, and outputs a structural implementation of the input circuit. The method presented here is similar to the covering algorithm used in multi-level optimizations; however, it is not based on Sum-of-Product form, or any specific input representation. Our experiments show that our approach is not only capable of automatically reproducing some known architectural implementations without any prior knowledge about the functionality of the circuit, but also, in some cases, it is able to discover completely new designs which we have not seen described in literature.

关键词： Iterative algorithms Logic circuits Circuit synthesis Adders Digital arithmetic computer science Libraries Circuit analysis Algorithm design and analysis Input variables

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A contamination aware droplet routing algorithm for digital microfluidic biochips

A contamination aware droplet routing algorithm for digital ...

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ieee international conference on computer-aided Design

作者： Tsung-Wei Huang Chun-Hsien Lin Tsung-Yi Ho Department of Computer Science and Information Engineering National Cheng Kung University Tainan Taiwan

In this paper, we propose a contamination aware droplet routing algorithm for digital microfluidic biochips (DMFBs). To reduce the routing complexities and the used cells, we first construct preferred routing tracks by analyzing the global moving vector of droplets to guide the droplet routing. To cope with contaminations within one subproblem, we first apply a k-shortest path routing technique to minimize the contaminated spots. Then, to take advantage of multiple wash droplets, we adopt a minimum cost circulation algorithm (MCC) for optimal wash-droplet routing to simultaneously minimize used cells and the cleaning time. Furthermore, a look-ahead prediction technique is used to determine the contaminations between successive subproblems. After that, we can simultaneously clean both contaminations within one subproblem and those between successive subproblems by using the MCC-based algorithm to reduce the execution time and the used cells. Based on four widely used bioassays, our algorithm reduces the used cells and the execution time significantly compared with the state-of-the-art algorithm.

关键词： Contamination Routing Microfluidics Electrodes Immune system Proteins computer science Cost function Cleaning Reservoirs

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PCRAMsim: System-level performance, energy, and area modeling for Phase-Change RAM 09

PCRAMsim: System-level performance, energy, and area modelin...

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ieee international conference on computer-aided Design

作者： Xiangyu Dong Norman P. Jouppi Yuan Xie Computer Science & Engineering Department Pennsylvania State University USA Exascale Computing Laboratory Hewlett Packard Laboratories USA

ISBN: (纸本)9781605588001

Phase-change random access memory (PCRAM) is an emerging memory technology with attractive features, such as fast read access, high density, and non-volatility. Because of these attractive properties, PCRAM is regarded as a promising candidate for future universal memories, and system-level designers could open up new design opportunities by leveraging this new memory technology. However, the majority of the PCRAM research has been at the device level, and system-level design space exploration using PCRAM is still in its infancy due to the lack of high-level modeling tools for PCRAM-based caches and memories. In this paper, we present a PCRAM model, called PCRAMsim, to bridge the gap between the device-level and system-level research on PCRAM technology. The model is validated against industrial PCRAM prototypes. This new PCRAMsim tool is expected to help boost PCRAM-related studies such as next-generation memory subsystems.

关键词： Phase change random access memory Random access memory Power system modeling Nonvolatile memory computer science Power engineering and energy Space technology System-level design Bridges Predictive models

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IPR: In-Place Reconfiguration for FPGA fault tolerance 09

IPR: In-Place Reconfiguration for FPGA fault tolerance

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ieee international conference on computer-aided Design

作者： Zhe Feng Yu Hu Lei He Rupak Majumdar Electrical Engineering Department University of California Los Angeles USA Computer Science Department University of California Los Angeles USA

ISBN: (纸本)9781605588001

We describe In-Place Reconfiguration (IPR) for LUT-based FPGAs, an algorithm that maximizes identical configuration bits for complementary inputs of a LUT thereby reducing the propagation of faults seen at a pair of complementary inputs. Based on IPR, we develop a fault-tolerant logic resynthesis algorithm which decreases the circuit fault rate while preserving functionality and topology of the LUT-based logic network. Since the topology is preserved, the resynthesis algorithm can be applied post-layout and without changes in physical design. Compared to the state-of-the-art academic technology mapper Berkeley ABC, IPR reduces the relative fault rate by 48% and increases MTTF by 1.94× with the same area and performance, and IPR combined with a previous fault-tolerant logic resynthesis algorithm (ROSE) reduces the relative fault rate by 49% and increases MTTF by 2.40× with 19% less area but same performance. The above improvement assumes a stochastic single fault and more improvement is expected for multi-fault models.

关键词： Intellectual property Field programmable gate arrays Fault tolerance Circuit faults Logic circuits Network topology Circuit topology Table lookup Reconfigurable logic Algorithm design and analysis

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Synthesizing sequential register-based computation with biochemistry

Synthesizing sequential register-based computation with bioc...

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ieee international conference on computer-aided Design

作者： Adam Shea Marc Riedel Brian Fett Keshab Parhi Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN USA

This paper presents a compilation strategy and a toolkit for biochemical reactions that perform sequential arithmetic computation on protein quantities, analogous to register-based computation in digital systems. From a Verilog-like input specification file, we generate biochemical reactions that produce output quantities as a function of input quantities, performing operations such as addition, subtraction, and multiplication. Sequential operations are implemented by transferring quantities between protein types, based on a clocking mechanism. Synthesis first is performed at a conceptual level, in terms of abstract biochemical reactions - a task analogous to technology-independent logic synthesis in circuit design. Then the results are mapped onto specific biochemical reactions, selected from libraries - a task analogous to technology mapping in circuit design. Our method targets the universal DNA substrate developed by Erik Win-free's group at Caltech as the experimental chassis. We demonstrate the algorithm on the synthesis of a variety of standard sequential functions: signal processing functions (FIR filters and IIR filters), vector multiplication, integration and differentiation. The designs are validated through transient stochastic simulation of the chemical kinetics.

关键词： Biochemistry Circuit synthesis Proteins Signal processing algorithms Digital arithmetic Digital systems Hardware design languages Clocks Logic design Logic circuits

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GREMA: Graph reduction based efficient mask assignment for double patterning technology 09

GREMA: Graph reduction based efficient mask assignment for d...

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ieee international conference on computer-aided Design

作者： Yue Xu Chris Chu Electrical and Computer Engineering Iowa State University Ames IA USA

ISBN: (纸本)9781605588001

Double patterning technology (DPT) has emerged as the most hopeful candidate for the next technology node of the ITRS roadmap. The goal of a DPT decomposer is to decompose the entire layout on each layer onto two masks. It assigns two features to different masks if their spacing is less than a predefined threshold. Besides, some features must be sliced and put onto two masks so that there would be a feasible solution for mask assignment. Such slicing will cause stitches that affect yield. So decomposer needs to minimize their number. In this paper, we formulate the DPT decomposition problem as a maximum cut problem. We propose an extremely efficient two-stage decomposition algorithm called GREMA. The first stage of GREMA generates a set of candidate stitches to ensure that feasible solutions exist for DPT decomposition. The second stage uses maximum cut to find the minimal set of stitches. Our decomposer is able to solve much larger realistic design problems. Experiments demonstrated that GREMA achieved great performance on resolving conflicts with greatly reduced runtime.

关键词： Runtime Lithography Permission Very large scale integration Resists Delay Etching Silicon Circuits Euclidean distance

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Gene-regulatory memories: Electrical-equivalent modeling, simulation and parameter identification 09

Gene-regulatory memories: Electrical-equivalent modeling, si...

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ieee international conference on computer-aided Design

作者： Yong Zhang Peng Li Department of Electrical and Computer Engineering Texas A and M University College Station TX USA

ISBN: (纸本)9781605588001

The development of gene-regulatory memory circuits provides key understandings of biological information storage and enables new biological applications. computer models and simulations can provide quantitative analysis and prediction of the behaviors and functions of genetic networks, thereby providing valuable verification and design guidance. In this paper, we model the nonlinear dynamics associated with various chemical reactions in gene-regulatory memory networks using chemical reaction equations. These reaction equations are mapped into a set of electrical-equivalent models and the network is simulated by an extended SPICE-like circuit simulation environment. Furthermore, we address the practical difficulty in direct characterization of network model parameters by developing a simulation-driven Bayesian framework for parameter identification. To ensure the reliable identification of key system properties, we propose a two-step structure-preserving parameter identification approach. The first step infers bistability, the most critical characteristics of a memory device; and the second step is geared towards identifying dynamical properties of the network while maintaining the identified bistability. We demonstrate the proposed approaches through extensive simulations that well agree with established biological understandings and identified networks that recreate measured circuit responses in a statistical sense.

关键词： Parameter estimation Biological system modeling Circuit simulation Computational modeling Predictive models Chemicals Nonlinear equations Application software Biology computing computer applications

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