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MOLES: Malicious off-chip leakage enabled by side-channels 09

MOLES: Malicious off-chip leakage enabled by side-channels

引用

ieee international conference on computer-aided Design

作者： Lang Lin Wayne Burleson Christof Paar Department of Electrical and Computer Engineering University of Massachusetts Amherst USA Horst Görtz Institute for IT Security Ruhr University of Bochum Germany

ISBN: (纸本)9781605588001

Economic incentives have driven the semiconductor industry to separate design from fabrication in recent years. This trend leads to potential vulnerabilities from untrusted circuit foundries to covertly implant malicious hardware trojans into a genuine design. Hardware trojans provide back doors for on-chip manipulation, or leak secret information off-chip once the compromised IC is deployed in the field. This paper explores the design space of hardware Trojans and proposes a novel technique, ¿Malicious Off-chip Leakage Enabled by Side-channels¿ (MOLES), which employs power side-channels to convey secret information off-chip. An experimental MOLES circuit is designed with fewer than 50 gates and is embedded into an Advanced Encryption Standard (AES) cryptographic circuit in a predictive 45 nm CMOS technology model. Engineered by a spread-spectrum technique, the MOLES technique is capable of leaking multi-bit information below the noise power level of the host IC to evade evaluators' detections. In addition, a generalized methodology for a class of MOLES circuits and design verification by statistical correlation analysis are presented. The goal of this work is to demonstrate the potential threats of MOLES on embedded system security. Nevertheless, MOLES could be constructively used for hardware authentication, fingerprinting and IP protection.

关键词： Hardware Space exploration Cryptography CMOS technology Integrated circuit noise Power generation economics Economic forecasting Electronics industry Fabrication Foundries

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CROP: Fast and effective congestion refinement of placement 09

CROP: Fast and effective congestion refinement of placement

引用

ieee international conference on computer-aided Design

作者： Yanheng Zhang Chris Chu Electrical and Computer Engineering Iowa State University Ames IA USA

ISBN: (纸本)9781605588001

Modern circuits become harder to route with the ever decreasing design features. Previous routability-driven placement techniques are usually tightly coupled with the underlying placers. So usually they cannot be easily integrated into various placement tools. In this paper, we propose a tool called CROP (Congestion Refinement of Placement) for mixed-size placement solutions. CROP is independent of any placer. It takes a legalized placement solution and then relocates the modules to improve routability without significantly disturbing the original placement solution. CROP interleaves a congestion-driven module shifting technique and a congestion-driven detailed placement technique. Basically the shifting technique targets at better allocating the routing resources. Shifting in each direction can be formulated as a linear program (LP) for resizing each G-Cell. Instead of solving the computationally expensive LP, we discover that the LP formulation could be relaxed and solved by a very efficient longest-path computation. Then the congestion-driven detailed placement technique is proposed to better distribute the routing demands. Congestion reduction is realized by weighting the HPWL with congestion coefficient during detailed placement. The experimental results show that CROP is capable of effectively alleviating the congestion for unroutable placement solutions. We apply it to placement solutions generated by four different placers on the ISPD05/06 placement benchmarks. Within a very short runtime, CROP greatly improves the routability and saves execution time for the routing stage after refinement.

关键词： Crops Routing White spaces Resource management Permission Design engineering Coupling circuits Runtime Lagrangian functions Wire

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REMiS: Run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set 09

REMiS: Run-time energy minimization scheme in a reconfigurab...

引用

ieee international conference on computer-aided Design

作者： Muhammad Shafique Lars Bauer Jörg Henkel Embedded Systems University of Karlsruhe Karlsruhe Germany

ISBN: (纸本)9781605588001

Reconfigurable processors provide a means to flexible and energy-aware computing. In this paper, we present a new scheme for runtime energy minimization (REMiS) as part of a dynamically recon-figurable processor that is exposed to run-time varying constraints like performance and footprint (i.e. amount of reconfigurable fabric). The scheme chooses an energy-minimizing set of so-called Special Instructions (considering leakage, dynamic, and reconfiguration energy) and then 'power-gates' a temporarily unused subset of the Special Instruction set. We provide a comprehensive evaluation for different technologies (ranging from 65 nm to 150 nm) and thereby show that our scheme is technology independent, i.e. it is beneficial for various technologies alike. By means of an H.264 video encoder we demonstrate that for certain performance constraints our scheme (applied to our in-house reconfigurable processor) achieves an allover energy saving of up to 40.8% (avg. 24.8%) compared to a performance-maximizing scheme. We also demonstrate that our scheme is equally beneficial to various other state-of-the-art reconfigurable processor architectures like Molen where it achieves energy savings of up to 48.7% (avg. 28.93%) at 65 nm. We have employed an H.264 encoder within this paper as an application in order to demonstrate the strengths of our scheme, since the H.264's complexity and run-time unpredictability present a challenging scenario for state-of-the-art architectures.

关键词： Runtime Field programmable gate arrays Fabrics Energy consumption computer aided instruction Containers Embedded system Embedded computing Reconfigurable logic Hardware

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DynaTune: Circuit-level optimization for timing speculation considering dynamic path behavior 09

DynaTune: Circuit-level optimization for timing speculation ...

引用

ieee international conference on computer-aided Design

作者： Lu Wan Deming Chen Electrical and Computer Engineering Department University of Illinois Urbana-Champaign USA

ISBN: (纸本)9781605588001

Traditional circuit design focuses on optimizing the static critical paths no matter how infrequently these paths are exercised dynamically. Circuit optimization is then tuned to the worst-case conditions to guarantee error-free computation but may also lead to very inefficient designs. Recently, there are processor works that over-clock the chip to achieve higher performance to the point where timing errors occur, and then error correction is performed either through circuit-level or microarchitecture-level techniques. This approach in general is referred to as Timing Speculation. In this paper, we propose a new circuit optimization technique "DynaTune" for timing speculation based on the dynamic behavior of a circuit. DynaTune optimizes the most dynamically critical gates of a circuit and improves the circuit's throughput under a fixed power budget. We test this proposed technique with two timing speculation schemes-Telescopic Unit (TU) and Razor Logic (RZ). Experimental results show that applying DynaTune on the Leon3 processor can increase the throughput of critical modules by up to 13% and 20% compared to the timing-speculative and non-timing-speculative results optimized by Synopsys Design Compiler, respectively. For MCNC benchmark circuits, DynaTune combined with TU can provide 9% and 20% throughput gains on average compared to timing-speculative and non-timing-speculative results optimized by Design Compiler. When combined with RZ, DynaTune can achieve 8% and 15% throughput gains on average for above experiments.

关键词： Timing Throughput Design optimization Circuit optimization Error correction Logic testing Optimizing compilers Circuit synthesis Microarchitecture Circuit testing

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2008 ieee/acm international conference on computer-aided Design digest of Technical Papers, ICCAD 2008

2008 IEEE/ACM International Conference on Computer-Aided Des...

引用

2008 international conference on computer-aided Design, ICCAD

ISBN: (纸本)9781424428205

The proceedings contain 127 papers. The topics discussed include: synthesis from multi-cycle atomic actions as a solution to the timing closure problem;on the numbers of variables to represent sparse logic functions;effective IR-drop reduction in at-speed scan testing using distribution-controlling X-identification;temperature-aware test scheduling for multiprocessor systems-on-chip;on capture power-aware test data compression for scan-based testing;yield-aware hierarchical optimization of large analog integrated circuits;model reduction via projection onto non-linear manifolds with applications to analog circuits and bio-chemical systems;algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure;delay-optimal simultaneous technology mapping and placement with applications to timing optimization;and a polynomial time approximation scheme for timing constrained minimum cost layer assignment.

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2008 ieee/acm international conference on computer-aided Design digest of Technical Papers, ICCAD 2008: Foreword

IEEE/ACM International Conference on Computer-Aided Design, ...

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ieee/acm international conference on computer-aided Design, digest of Technical Papers, ICCAD 2008年

作者： Nassif, Sani R. Roychowdhury, Jaijeet

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ISBN: (纸本)9781424428205

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Graphene nanoribbon FETs: Technology exploration and CAD

Graphene nanoribbon FETs: Technology exploration and CAD

引用

2008 international conference on computer-aided Design, ICCAD

作者： Mohanram, Kartik Guo, Jing Department of Electrical and Computer Engineering Rice University Houston United States Department of Electrical and Computer Engineering University of Florida Gainesville United States

ISBN: (纸本)9781424428205

Graphene nanoribbon FETs (GNRFETs) have emerged as a promising candidate for nanoelectronics applications. This paper summarizes (i) current understanding and prospects for GNRFETs as ultimately scaled, ideal ballistic transistors, (ii) physics-based modeling of GNRFETs to support circuit design and CAD, and (iii) variability and defects in GNRs and their impact on GNRFET circuit performance and reliability.

关键词： Graphene

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On the modeling of resistance in Graphene Nanoribbon (GNR) for future interconnect applications

On the modeling of resistance in Graphene Nanoribbon (GNR) f...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Ragheb, Tamer Massoud, Yehia Electrical and Computer Engineering Department Rice University Houston TX 77005 United States

ISBN: (纸本)9781424428205

In this paper, we present a comprehensive model for the resistance in graphene nanoribbon (GNR) interconnects. We use the recent experimental and theoretical results to model the impact of stacking of graphene layers in multi-layer GNR interconnects. We compare the resistance of GNR interconnects with both single-walled carbon nanotube (SWCNT) bundle interconnects and conventional copper Interconnects. Our simulation results demonstrate the performance superiority of multi-layer GNR interconnects over conventional copper interconnects at small widths (

关键词： Copper

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Guiding global placement with wire density

Guiding global placement with wire density

引用

2008 international conference on computer-aided Design, ICCAD

作者： Tsota, Kalliopi Koh, Cheng-Kok Balakrishnan, Venkataramanan School of Electrical and Computer Engineering Purdue University West Lafayette IN 47907-2035 United States

ISBN: (纸本)9781424428205

This paper presents an efficient technique for the estimation of the routed wirelength during global placement using the wire density of the net. The proposed method identifies congested regions of the chip and incorporates the model of the routed wirelength into the objective function in order to effectively alleviate these regions from congestion. The method is integrated in the analytical placement framework and the two-level structure improves the scalability of the placer and speeds up the algorithm. The proposed analytical placer provides the best-so-far average routed wirelength in the IBM version2 benchmark suite.

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Comprehensive procedure for fast and accurate coupled oscillator network simulation

Comprehensive procedure for fast and accurate coupled oscill...

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2008 international conference on computer-aided Design, ICCAD

作者： Bhansali, Prateek Srivastava, Shweta Lai, Xiaolue Roychowdhury, Jaijeet Department of Electrical and Computer Engineering University of Minnesota

ISBN: (纸本)9781424428205

Coupled oscillator networks occur in various domains such as biology, astrophysics and electronics. In this paper, we present a comprehensive procedure for rapid and accurate simulation of large coupled oscillator networks using widely accepted, fully-nonlinear Perturbation Projection Vector (PPV) phase macromodels. We validate our method against full simulation of 2020 coupled network of Brusselator biochemical oscillator and obtain computational speedups of 170x over full simulation. Furthermore, we apply the method to study self-organization phenomenon of Brusselator under asymmetric coupling and time period variations.

关键词： Astrophysics

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