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2024 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-Flop 24

2024 ICCAD CAD Contest Problem B: Power and Timing Optimizat...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Yang, Sheng-Wei Hsu, Jhih-Wei Li, Ting Wei Chen, Tzu-Hsuan Shen, Chin-Fang Cindy Synopsys Inc. No. 25 Industry East Road IV Science-Based Industrial Park Hsinchu Taiwan

ISBN: (纸本)9798400710773

In modern designs, timing performance, power, and area constraints (PPA) are the three major metrics for physical design. 2024 ICCAD CAD Contest Problem B investigates the optimization of power, area, and timing in modern semiconductor designs through the strategic use of multibit flip-flops. By banking flip-flops, more area can be freed up, and also efficiently reduce power consumption and reduce net routing complexity. While multibit flip-flop banking has been effective in reducing power and area, it could negatively impact timing performance in critical paths, thus multibit flip-flop debanking could be performed to alleviate timing critical paths. 2024 ICCAD CAD Contest Problem B presents a challenge where participants must optimize the virtual designs by dynamically applying banking and debanking techniques to achieve optimized trade-offs among PPA. © 2024 Copyright is held by the owner/author(s).

关键词： computer aided logic design

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Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits 24

Joint Placement Optimization for Hierarchical Analog/Mixed-S...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Gao, Xiaohan Zhang, Haoyi Liu, Bingyang Lin, Yibo Wang, Runsheng Huang, Ru School of Computer Science Peking University China School of Integrated Circuits Peking University China Institute of EDA Peking University China School of EECS Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

The performance of Analog/Mixed Signal (AMS) circuits is highly dependent on the meticulous layout implementation. To meet performance and area requirements, real-world AMS layout design is thoroughly optimized to consider circuit hierarchy and a multitude of factors, such as system signal flow and regularity. Circuit hierarchy and these factors impose complicated constraints, which challenge layout design flow. In this paper, we propose a systematic AMS placement framework to address the challenges through joint optimization. We implement our framework in a unified and highly extensible workflow and validate our framework with broad types of real-world AMS circuits. Experiments show that our framework achieves promising results in both efficiency and quality. © 2024 Copyright is held by the owner/author(s).

关键词： Timing circuits

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Spiking Transformer Hardware Accelerators in 3D Integration 24

Spiking Transformer Hardware Accelerators in 3D Integration

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Xu, Boxun Hwang, Junyoung Vanna-Iampikul, Pruek Lim, Sung Kyu Li, Peng Department of Electrical and Computer Engineering University of California Santa BarbaraCA United States Department of Electrical and Computer Engineering Georgia Institute of Technology GA United States Department of Electrical Engineering Burapha University Chonburi Thailand

ISBN: (纸本)9798400710773

Spiking neural networks (SNNs) are powerful models of spatiotemporal computation and are well suited for deployment on resource-constrained edge devices and neuromorphic hardware due to their low power consumption. Leveraging attention mechanisms similar to those found in their artificial neural network counterparts, recently emerged spiking transformers have showcased promising performance and efficiency by capitalizing on the binary nature of spiking operations. Recognizing the current lack of dedicated hardware support for spiking transformers, this paper presents the first work on 3D spiking transformer hardware architecture and design methodology. We present an architecture and physical design co-optimization approach tailored specifically for spiking transformers. Through memory-on-logic and logic-on-logic stacking enabled by 3D integration, we demonstrate significant energy and delay improvements compared to conventional 2D CMOS integration. © 2024 Copyright is held by the owner/author(s).

关键词： CMOS integrated circuits

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EasyPart: An Effective and Comprehensive Hypergraph Partitioner for FPGA-based Emulation 24

EasyPart: An Effective and Comprehensive Hypergraph Partitio...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Tong, Shengbo Li, Haoyuan Xu, Jiahao Pei, Chunyan Yu, Wenjian Liu, Shengjun Shen, Jian Dept. Computer Science & Tech. BNRist Tsinghua Univ. Beijing China HyperSilicon Inc. Wuxi China

ISBN: (纸本)9798400710773

Logic verification becomes more and more important for the design of large-scale digital integrated circuits (ICs). This makes FPGA-based hardware emulation an imperative step in the design flow, and how to effectively partition and map the circuit netlist into the multi-FPGA system (MFS) for emulation is of concern. In this paper, we present EasyPart, an effective and comprehensive hypergraph partitioner for the FPGA-based hardware emulation. EasyPart can handle the practical constraints in the MFS for logic emulation and includes novel techniques for pursuing minimum hop during topology-driven partitioning and treating the interconnection constraints. We have evaluated EasyPart against state-of-the-art partitioners on public benchmarks. The results show that EasyPart can reduce the cutsize with a comparable or shorter runtime. EasyPart is capable of finding non-hop solutions with better robustness and performance compared to previous work. It also achieves significant improvements in terms of time division multiplexing (TDM) ratio and maximum hop when tested on industrial cases. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine 24

Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Gonul, Yilmaz Ege Taskin, Baris Department of Electrical and Computer Engineering Drexel University PhiladelphiaPA United States

ISBN: (纸本)9798400710773

This paper presents a coupled ring oscillator based Potts machine to solve NP-hard combinatorial optimization problems (COPs). Potts model is a generalization of the Ising model, capturing multivalued spins in contrast to the binary-valued spins allowed in the Ising model. Similar to recent literature on Ising machines, the proposed architecture of Potts machines implements the Potts model with interacting spins represented by coupled ring oscillators. Unlike Ising machines which are limited to two spin values, Potts machines model COPs that require a larger number of spin values. A major novelty of the proposed Potts machine is the utilization of the N-SHIL (Sub-Harmonic Injection Locking) mechanism, where multiple stable phases are obtained from a single (i.e. ring) oscillator. In evaluation, 3-coloring problems from the DIMACS SATBLIB benchmark and two randomly generated larger problems are mapped to the proposed architecture. The proposed architecture is demonstrated to solve problems of varying size with 89% to 92% accuracy averaged over multiple iterations. The simulation results show that there is no degradation in accuracy, no significant increase in solution time, and only a linear increase in power dissipation with increasing problem sizes up to 2000 nodes. © 2024 Copyright is held by the owner/author(s).

关键词： Ising model

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HDXpose: Harnessing Hyperdimensional Computing’s Explainability for Adversarial Attacks 24

HDXpose: Harnessing Hyperdimensional Computing’s Explainabi...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Asgarinejad, Fatemeh Pozina, Flavio Gungor, Onat Rosing, Tajana Aksanli, Baris Department of Computer Science and Engineering UC San Diego La Jolla CA92093 United States Department of Electrical and Computer Engineering SDSU CA92182 United States

ISBN: (纸本)9798400710773

Hyperdimensional Computing (HDC), a promising alternative to address the limitations of edge devices, is not exempt from the security challenges confronted by machine learning algorithms, in particular, adversarial attacks. The limited body of research exploring the security implications of HDC overlooks its inherent algorithm. In this paper, we propose a novel and effective adversarial attack technique targeting HDC. Our approach analyzes and prioritizes the impact of input features as well as encoded elements on decision boundaries and perturbs the input towards incorrect decisions in a guided manner. We evaluate our method on different datasets and attack models (i.e., untargeted/targeted, white-box/gray-box). Experimental results indicate that our proposed design, HDXpose, significantly outperforms the state-of-the-art attack techniques by achieving higher success rate with smaller distortion and execution time, rendering its efficacy for real-time attack generation. © 2024 Copyright is held by the owner/author(s).

关键词： Adversarial machine learning

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Layout-level Hardware Trojan Prevention in the Context of Physical Design 24

Layout-level Hardware Trojan Prevention in the Context of Ph...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Tong, Xingyu Chen, Guohao Wei, Min Cai, Zhijie Zou, Peng Lin, Zhifeng Chen, Jianli State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China School of Microelectronics Fudan University Shanghai China Shanghai LEDA Technology Co. Ltd. Shanghai China School of Mathematics and Statistics Fuzhou University Fuzhou China

ISBN: (纸本)9798400710773

A growing recognition of potential vulnerabilities to layout-level Hardware Trojan (HT) attacks has spurred significant research efforts aimed at enhancing the resilience of ICs against such threats. However, traditional hardware security has been predominantly concerned with defensive measures, often overlooking the original key metrics in physical design evaluation: power, performance, and area (PPA). This study introduces an automated methodology incorporating HT considerations into the practical physical design process. Utilizing a Bayesian optimization framework, it effectively navigates the operation of commercial physical implementation tools in the solution space of hyper-parameter settings. Innovative strategies inspired by mosaic techniques, such as cell shifting and buffer insertion, realize additional improvements in layout-level trojan prevention. Comparative evaluations have shown that our approach outperforms leading entries from the ISPD 2023 Contest in terms of PPA and HT prevention metrics, thereby providing significant insights into the synergy between these critical factors. © 2024 Copyright is held by the owner/author(s).

关键词： computer viruses

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ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured Sparsity 24

ChatOPU: An FPGA-based Overlay Processor for Large Language ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Zhao, Tiandong Lu, Shaoqiang Wu, Chen He, Lei University of California Los Angeles United States Shanghai Jiao Tong University China Ningbo Institute of Digital Twin Eastern Institute of Technology China

ISBN: (纸本)9798400710773

Large language models (LLMs) have achieved notable success on many applications with increasingly tremendous parameters and computations. While hardware accelerators on Transformer-based models have been extensively studied, recent work mainly assumes structured model pruning and does not work well for unstructured sparsity that could lead to more parameter and computation reduction. The reason behind is that it is difficult to exploit data reuse from the unstructured sparsity, leaving hardware underutilized. This paper proposes ChatOPU, an FPGA-based overlay processor for LLMs, to support unstructured model pruning with better data reuse. First, we propose a new diagonal dataflow on a systolic array to obtain efficient data reuse for both sparse and dense matrix multiplication. Second, we develop efficient encoding and decoding for the sparse parameters to save off-chip memory traffic. Moreover, we boost the off-chip bandwidth utilization with pinned on-chip KV cache allocation and coalesced access throughout the LLM inference. Experimental results show that ChatOPU on Xilinx U200 FPGA outperforms GPU and other FPGA-based accelerators on token/s by 2.29× and 1.63× on LLMs with unstructured sparsity across different input and output sequence lengths. © 2024 Copyright is held by the owner/author(s).

关键词： Storage allocation (computer)

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MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management 24

MORPH: More Robust ASIC Placement for Hybrid Region Constrai...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Mai, Jing Zhang, Zuodong Lin, Yibo Wang, Runsheng Huang, Ru School of Computer Science Peking University China School of Integrated Circuits Peking University China Institute of EDA Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

Modern ASIC placement tools encompass three categories of region constraints: default regions, fence regions, and guide regions. Region constraints pose significant challenges to existing placement algorithms, compromising the versatility and robustness required for diverse placement workloads. In this work, we propose MORPH, a more robust ASIC placer designed for hybrid region constraints. We integrate hybrid region constraints into a unified multi-electrostatic formulation that features a shared electrostatics model and a binary-lifting-based region pruning algorithm. We develop a more robust nonlinear placement framework that includes second-order information and a hybrid-region-aware legalization algorithm to address convergence issues. Experiments on the ISPD 2015 benchmark suite demonstrate 5.6-14.3% HPWL improvement and 10-24% overflow reduction compared to state-of-the-art region-aware placers. Further experiments on the ISPD 2015 benchmark suite and its variants show that the proposed techniques can achieve over 30% HPWL improvement and up to a twofold reduction in overflow with more stable convergence. © 2024 Copyright is held by the owner/author(s).

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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement 24

Physically Aware Synthesis Revisited: Guiding Technology Map...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption. © 2024 Copyright is held by the owner/author(s).

关键词： Logic design

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