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检索条件"任意字段=IEEE/ACM International Conference on Computer Aide Digest"
890 条 记 录,以下是11-20 订阅
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2024 ICCAD CAD Contest Problem B: Power and Timing Optimization Using Multibit Flip-Flop  24
2024 ICCAD CAD Contest Problem B: Power and Timing Optimizat...
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Yang, Sheng-Wei Hsu, Jhih-Wei Li, Ting Wei Chen, Tzu-Hsuan Shen, Chin-Fang Cindy Synopsys Inc. No. 25 Industry East Road IV Science-Based Industrial Park Hsinchu Taiwan
In modern designs, timing performance, power, and area constraints (PPA) are the three major metrics for physical design. 2024 ICCAD CAD Contest Problem B investigates the optimization of power, area, and timing in mo... 详细信息
来源: 评论
Joint Placement Optimization for Hierarchical Analog/Mixed-Signal Circuits  24
Joint Placement Optimization for Hierarchical Analog/Mixed-S...
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Gao, Xiaohan Zhang, Haoyi Liu, Bingyang Lin, Yibo Wang, Runsheng Huang, Ru School of Computer Science Peking University China School of Integrated Circuits Peking University China Institute of EDA Peking University China School of EECS Peking University China Beijing Advanced Innovation Center for Integrated Circuits China
The performance of Analog/Mixed Signal (AMS) circuits is highly dependent on the meticulous layout implementation. To meet performance and area requirements, real-world AMS layout design is thoroughly optimized to con... 详细信息
来源: 评论
Spiking Transformer Hardware Accelerators in 3D Integration  24
Spiking Transformer Hardware Accelerators in 3D Integration
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Xu, Boxun Hwang, Junyoung Vanna-Iampikul, Pruek Lim, Sung Kyu Li, Peng Department of Electrical and Computer Engineering University of California Santa BarbaraCA United States Department of Electrical and Computer Engineering Georgia Institute of Technology GA United States Department of Electrical Engineering Burapha University Chonburi Thailand
Spiking neural networks (SNNs) are powerful models of spatiotemporal computation and are well suited for deployment on resource-constrained edge devices and neuromorphic hardware due to their low power consumption. Le... 详细信息
来源: 评论
EasyPart: An Effective and Comprehensive Hypergraph Partitioner for FPGA-based Emulation  24
EasyPart: An Effective and Comprehensive Hypergraph Partitio...
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Tong, Shengbo Li, Haoyuan Xu, Jiahao Pei, Chunyan Yu, Wenjian Liu, Shengjun Shen, Jian Dept. Computer Science & Tech. BNRist Tsinghua Univ. Beijing China HyperSilicon Inc. Wuxi China
Logic verification becomes more and more important for the design of large-scale digital integrated circuits (ICs). This makes FPGA-based hardware emulation an imperative step in the design flow, and how to effectivel... 详细信息
来源: 评论
Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine  24
Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Gonul, Yilmaz Ege Taskin, Baris Department of Electrical and Computer Engineering Drexel University PhiladelphiaPA United States
This paper presents a coupled ring oscillator based Potts machine to solve NP-hard combinatorial optimization problems (COPs). Potts model is a generalization of the Ising model, capturing multivalued spins in contras... 详细信息
来源: 评论
HDXpose: Harnessing Hyperdimensional Computing’s Explainability for Adversarial Attacks  24
HDXpose: Harnessing Hyperdimensional Computing’s Explainabi...
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Asgarinejad, Fatemeh Pozina, Flavio Gungor, Onat Rosing, Tajana Aksanli, Baris Department of Computer Science and Engineering UC San Diego La Jolla CA92093 United States Department of Electrical and Computer Engineering SDSU CA92182 United States
Hyperdimensional Computing (HDC), a promising alternative to address the limitations of edge devices, is not exempt from the security challenges confronted by machine learning algorithms, in particular, adversarial at... 详细信息
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Layout-level Hardware Trojan Prevention in the Context of Physical Design  24
Layout-level Hardware Trojan Prevention in the Context of Ph...
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Tong, Xingyu Chen, Guohao Wei, Min Cai, Zhijie Zou, Peng Lin, Zhifeng Chen, Jianli State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China School of Microelectronics Fudan University Shanghai China Shanghai LEDA Technology Co. Ltd. Shanghai China School of Mathematics and Statistics Fuzhou University Fuzhou China
A growing recognition of potential vulnerabilities to layout-level Hardware Trojan (HT) attacks has spurred significant research efforts aimed at enhancing the resilience of ICs against such threats. However, traditio... 详细信息
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ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured Sparsity  24
ChatOPU: An FPGA-based Overlay Processor for Large Language ...
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Zhao, Tiandong Lu, Shaoqiang Wu, Chen He, Lei University of California Los Angeles United States Shanghai Jiao Tong University China Ningbo Institute of Digital Twin Eastern Institute of Technology China
Large language models (LLMs) have achieved notable success on many applications with increasingly tremendous parameters and computations. While hardware accelerators on Transformer-based models have been extensively s... 详细信息
来源: 评论
MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management  24
MORPH: More Robust ASIC Placement for Hybrid Region Constrai...
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Mai, Jing Zhang, Zuodong Lin, Yibo Wang, Runsheng Huang, Ru School of Computer Science Peking University China School of Integrated Circuits Peking University China Institute of EDA Peking University China Beijing Advanced Innovation Center for Integrated Circuits China
Modern ASIC placement tools encompass three categories of region constraints: default regions, fence regions, and guide regions. Region constraints pose significant challenges to existing placement algorithms, comprom...
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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement  24
Physically Aware Synthesis Revisited: Guiding Technology Map...
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43rd international conference on computer-aided Design, ICCAD 2024
作者: Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States
A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing a... 详细信息
来源: 评论