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A voltage-frequency island aware energy optimization framework for networks-on-chip

A voltage-frequency island aware energy optimization framewo...

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2008 international conference on computer-aided Design, ICCAD

作者： Wooyoung, Jang Duo, Ding Pan, David Z. Department of Electrical and Computer Engineering University of Texas at Austin Austin TX 78712 United States

ISBN: (纸本)9781424428205

In this paper, we present a partitioning, mapping, and routing optimization framework for energy-efficient VFI (Voltage-Frequency Island) based Network-on-Chip. Unlike the recent work [10] which only performs partitioning together with voltage-frequency assignment for a given mesh network layout, our framework consists of three key VFI-aware components, i.e., VFI-aware partitioning, VFI-aware mapping, and VFI-aware routing. Thus our technique effectively reduces VFI overheads such as mixed clock FIFOs and voltage level converters by over 82% and energy consumption by over 9% compared with the previous state-of-art works [10].

关键词： Network-on-chip

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Power supply signal calibration techniques for improving detection resolution to hardware trojans

Power supply signal calibration techniques for improving det...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Rad, Reza M. Wang, Xiaoxiao Tehranipoor, Mohammad Plusquellic, Jim Department of CSEE Univ. of Maryland Baltimore Campus Department of Electrical and Computer Engineering Univ. of Connecticut Department of Electrical and Computer Engineering Univ. of New Mexico

ISBN: (纸本)9781424428205

Chip design and fabrication is becoming increasingly vulnerable to malicious activities and alternations with globalization. An adversary can introduce a Trojan designed to disable and/or destroy a system at some future time (Time Bomb) or the Trojan may serve to leak confidential information covertly to the adversary. This paper proposes a taxonomy for Trojan classification and then describes a statistical approach for detecting hardware Trojans that is based on the analysis of an ICs power supply transient signals. A key component to improving the resolution of power analysis techniques to Trojans is calibrating for process and test environment (PE) variations. The main focus of this research is on the evaluation of four signal calibration techniques, each designed to reduce the adverse impact of PE variations on our statistical Trojan detection method.

关键词： Calibration

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On capture power-aware test data compression for scan-based testing

On capture power-aware test data compression for scan-based ...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Li, Jia Liu, Xiao Zhang, Yubin Hu, Yu Li, Xiaowei Xu, Qiang Key Laboratory of Computer System and Architecture ICT CAS Beijing China Graduate University Chinese Academy of Sciences Beijing China Deptartment of Computer Science and Engineering Chinese University of Hong Kong Shatin N.T. Hong Kong

ISBN: (纸本)9781424428205

Large test data volume and high test power are two of the major concerns for the industry when testing large integrated circuits. With given test cubes in scan-based testing, the "don't-care" bits can be exploited for test data compression and/or test power reduction. Prior work either targets only one of these two issues or considers to reduce test data volume and scan shift power together. In this paper, we propose a novel capture power-aware test compression scheme that is able to keep scan capture power under a safe limit with little loss in test compression ratio. Experimental results on benchmark circuits demonstrate the efficacy of the proposed approach.

关键词： Power management

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Thermal-aware floorplanning for task migration enabled active sub-threshold leakage reduction

Thermal-aware floorplanning for task migration enabled activ...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Mogal, Hushrav D. Bazargan, Kia Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN 55455 United States

ISBN: (纸本)9781424428205

This paper presents a new approach to active sub-threshold leakage reduction using task migration. The main idea is to replicate a hot module in a design so as to actively migrate its computation at regular intervals, reducing the on-chip temperature and thereby the sub-threshold leakage. We observe that choosing which blocks to migrate and their placement in a floorplan is a chicken-and-egg problem. To solve this, we propose a two step floorplanning methodology, wherein, given a base floorplan, we first choose the modules to replicate and then effectively utilize the deadspaces in it by exploiting the lateral conduction of heat in the floorplan to place a module's replica. With an optimized floorplan, using task migration we obtain an average savings of 29% in the active sub-threshold leakage at the expense of about 6% additional area.

关键词： Integrated circuit design

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NTHU-route 2.0: A fast and stable global router

NTHU-route 2.0: A fast and stable global router

引用

2008 international conference on computer-aided Design, ICCAD

作者： Chang, Yen-Jung Lee, Yu-Ting Wang, Ting-Chi Department of Computer Science National Tsing Hua University Hsinchu 30013 Taiwan

ISBN: (纸本)9781424428205

We present in this paper a fast and stable global router called NTHU-Route 2.0 that improves the solution quality and runtime of a state-of-the-art router, NTHU-Route, by the following enhancements: (1) a new history based cost function, (2) new ordering methods for congested region identification and rip-up and reroute, and (3) two implementation techniques. The experimental results show that NTHU-Router 2.0 solves all ISPD98 benchmarks with very good quality. Moreover, it routes 7 of 8 ISPD07 benchmarks without any overflow. In particular, for one of the ISPD07 benchmarks which are thought to be difficult cases previously, NTHU-Route 2.0 can completely eliminate its total overflow. NTHU-Route 2.0 also successfully solves 12 of 16 ISPD08 benchmarks without causing any overflow.

关键词： Cost functions

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Context-sensitive static transistor-level IR analysis

Context-sensitive static transistor-level IR analysis

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2008 international conference on computer-aided Design, ICCAD

作者： Guo, Weiqing Zhong, Yu Burd, Tom Silicon Design CAD Advanced Micro Devices Sunnyvale CA 94085 United States Dept. of Electrical and Computer Engineering Univ. of Illinois at Urbana-Champaign Urbana IL 61801 United States

ISBN: (纸本)9781424428205

With advances in semiconductor process technology, chip power density has dramatically increased, making power grid integrity a critical concern at all stages of the design process. Given the inherent difficulty of capturing worst-case IR drops for all logic gates with dynamic vectors, a static flow is essential for verifying grid integrity on complex chip designs, especially microprocessors. A novel static transistor-level IR drop analysis flow which significantly reduces the conservatism of other static flows is presented. The key feature of this flow is a fast NAND decision diagram (NDD) algorithm, a lightweight variant of a boolean decision diagram (BDD) with the capacity to effectively process device transition exclusions in a per logical-device, context-sensitive fashion, thereby radically reducing the conservatism typical of static analysis.

关键词： Static analysis

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System-level thermal aware design of applications with uncertain execution time

System-level thermal aware design of applications with uncer...

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2008 international conference on computer-aided Design, ICCAD

作者： Zhang, Sushu Chatha, Karam S. Department of Computer Science and Engineering Arizona State University Tempe AZ 85287 United States

ISBN: (纸本)9781424428205

The paper introduces the problem of system-level thermal aware design of applications with uncertain run time on an embedded processor equipped with dynamic voltage/frequency scaling features. The problem takes as inputs a task sequence, cycle time distribution of each task, and processor thermal model. The solution specifies a voltage/frequency assignment to the tasks such that the expected latency is minimized subject to the probability that the peak temperature constraint is not violated is no less than a designer specified value. We prove that the problem is at least NP-hard, and present optimal and (1 + Ε) fully polynomial time approximation scheme as solutions. To the best of our knowledge, this paper is the first work that addresses the stochastic version of the system-level thermal-aware design problem. We evaluate the effectiveness of our techniques by experimenting with realistic and synthetic benchmarks.

关键词： Stochastic systems

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A framework for predictive dynamic temperature management of microprocessor systems

A framework for predictive dynamic temperature management of...

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2008 international conference on computer-aided Design, ICCAD

作者： Khan, Omer Kundu, Sandip Department of Electrical and Computer Engineering University of Massachusetts Amherst Amherst MA 01002 United States

ISBN: (纸本)9781424428205

The sustained push for performance, transistor count and instruction level parallelism has reached a point where IC thermal issues are at the forefront of design constraints. Many of the current systems deploy dynamic voltage and frequency scaling (DVFS) to address thermal emergencies. DVFS has certain limitations in terms of response lag, scalability and being reactive. On the other hand, several hardware based control theoretic schemes have been proposed to deliver optimal performance, but such schemes come at high cost and lack flexibility and scalability. In this paper, we present an alternative thermal monitoring and management system that utilizes software and hardware components, based on virtual machine concept The proposed scheme delivers targeted, localized, and preemptive thermal management at low cost, adapts well to a multitasking environment, while delivering maximum performance under thermal stress.

关键词： Scalability

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FastRoute3.0: A fast and high quality global router based on virtual capacity 08

FastRoute3.0: A fast and high quality global router based on...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Yanheng, Zhang Yue, Xu Chu, Chris Department of Electrical and Computer Engineering Iowa State University Ames IA 50011 United States

ISBN: (纸本)9781424428205

As an easily implemented approach, ripup and reroute has been employed by most of today's global routers, which iteratively applies maze routing to refine solution quality. But traditional maze routing is susceptible to get stuck at local optimal results. In this work, we will present a fast and high quality global router FastRoute3.0, with the new technique named virtual capacity. Virtual capacity is proposed to guide the global router at maze routing stage to achieve higher quality results in terms of overflow and runtime. During maze routing stage, virtual capacity works as a substitute for the real edge capacity in calculating the maze routing cost. There are two sub techniques included: (1) virtual capacity initialization, (2) virtual capacity update. Before the maze routing stage, FastRoute3.0 initializes the virtual capacity by subtracting the predicted overflow generated by adaptive congestion estimation (ACE) from the real edge capacity. And in the following maze routing iterations, we further reduce the virtual capacity by the amount of existing overflow(edge usage minus real edge capacity) for the edges that are still congested. To avoid excessive "pushing-away" of routing wires, the virtual capacity is increased by a fixed percentage of the existing overflow if edge usage is smaller than real edge capacity. Experimental results show that FastRoute3.0 is highly proficient dealing with ISPD98, ISPD07 and ISPD08 benchmark suites. The results outperform published ripup and reroute based academic global routers in both routability and runtime. In particular, (1) FastRoute3.0 completes routing all the ISPD98 benchmarks. (2) For ISPD07 and ISPD08 global routing contest benchmarks, it generates 12 out of 16 congestion free solutions. (3) The total runtime is enhanced greatly.

关键词： Routers

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Breaking the simulation barrier: SRAM evaluation through norm minimization

Breaking the simulation barrier: SRAM evaluation through nor...

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2008 international conference on computer-aided Design, ICCAD

作者： Dolecek, Lara Qazi, Masood Shah, Devavrat Chandrakasan, Anantha Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA 02139 United States

ISBN: (纸本)9781424428205

With process variation becoming a growing concern in deep submicron technologies, the ability to efficiently obtain an accurate estimate of failure probability of SRAM components is becoming a central issue. In this paper we present a general methodology for a fast and accurate evaluation of the failure probability of memory designs. The proposed statistical method, which we call importance sampling through norm minimization principle, reduces the variance of the estimator to produce quick estimates. It builds upon the importance sampling, while using a novel norm minimization principle inspired by the classical theory of Large Deviations. Our method can be applied for a wide class of problems, and our illustrative examples are the data retention voltage and the read/write failure tradeoff for 6T SRAM in 32 nm technology. The method yields computational savings on the order of 10000x over the standard Monte Carlo approach in the context of failure probability estimation for SRAM considered in this paper.

关键词： Static random access storage

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