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Robust reconfigurable filter design using analytic variability quantification techniques

Robust reconfigurable filter design using analytic variabili...

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2008 international conference on computer-aided Design, ICCAD

作者： Nieuwoudt, Arthur Kawa, Jamil Massoud, Yehia Department of Electrical and Computer Engineering Rice University Houston TX United States Advanced Technology Group Synopsys Inc. Mountain View CA United States

ISBN: (纸本)9781424428205

In this paper, we develop a variability-aware design methodology for reconfigurable filters used in multi-standard wireless systems. To model the impact of statistical circuit component variations on the predicted manufacturing yield, we implement several different analytic variability quantification techniques based on a double-sided implementation of the first and second order reliability methods (FORM and SORM), which provide several orders of magnitude improvement in computational complexity over statistical sampling methods. Leveraging these efficient analytic variability quantification techniques, we employ an optimization approach using Sequential Quadratic Programming to simultaneously determine the fixed and tunable/switchable circuit element values in an arbitrary-order canonical filter to improve the overall robustness of the filter design when statistical variations are present. The results indicate that reconfigurable filters and impedance matching networks designed using the proposed methodology meet the specified performance requirements with a 26% average absolute yield improvement over circuits designed using deterministic techniques.

关键词： Sampling

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Robust FPGA resynthesis based on fault-tolerant boolean matching

Robust FPGA resynthesis based on fault-tolerant boolean matc...

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2008 international conference on computer-aided Design, ICCAD

作者： Hu, Yu Feng, Zhe He, Lei Majumdar, Rupak Electrical Engineering Department University of California Los Angeles United States Computer Science Department University of California Los Angeles United States

ISBN: (纸本)9781424428205

We present FPGA logic synthesis algorithms for stochastic fault rate reduction in the presence of both permanent and transient defects. We develop an algorithm for fault tolerant Boolean matching (FTBM), which exploits the flexibility of the LUT configuration to maximize the stochastic yield rate for a logic function. Using FTBM, we propose a robust resynthesis algorithm (ROSE) which maximizes stochastic yield rate for an entire circuit. Finally, we show that existing PLB (programmable logic block) templates for area-aware Boolean matching and logic resynthesis are not effective for fault tolerance, and propose a new robust template with path re-convergence. Compared to the state-of-the-art academic technology mapper Berkeley ABC, ROSE using the proposed robust PLB template reduces the fault rate by 25% with 1% fewer LUTs, and increases MTBF (mean time between failures) by 31%, while preserving the optimal logic depth.

关键词： Field programmable gate arrays (FPGA)

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Fault tolerant placement and defect reconfiguration for nano-FPGAs

Fault tolerant placement and defect reconfiguration for nano...

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2008 international conference on computer-aided Design, ICCAD

作者： Agarwal, Amit Cong, Jason Tagiku, Brian Department of Computer Science University of California at Los Angeles Los Angeles CA United States

ISBN: (纸本)9781424428205

When manufacturing nano-devices, defects are a certainty and reliability becomes a critical issue. Until now, the most pervasive methods used to address reliability, involve injecting spare resources. However, these methods use predetermined spare placement that is not optimized for each netlist. This is the first work (to the best of our knowledge) that addresses the problem of fault tolerance for nano-FPGAs at the placement stage;fault tolerant placements are generated that are amenable to fast defect reconfiguration through replacement of defective logic elements with spares. We propose a simulatedannealing based placement algorithm that produces placements with the objective of maximizing the chances of successful recovery from faults in logic elements within the circuit's timing constraints. In addition, our study of the fault reconfiguration problem shows it is NP-Complete, and we propose a fast scheme for achieving a good reconfiguration solution for a random or clustered fault map. Experimental results show that these techniques can increase the probability of successful fault reconfiguration by 55% (compared to a uniform spare distribution scheme), without significantly degrading the circuit performance.

关键词： Defects

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Yield-aware hierarchical optimization of large analog integrated circuits

Yield-aware hierarchical optimization of large analog integr...

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2008 international conference on computer-aided Design, ICCAD

作者： Yu, Guo Li, Peng Department of Electrical and Computer Engineering Texas A and M University College Station TX 77843 United States

ISBN: (纸本)9781424428205

Hierarchical optimization using building circuit block pareto performance models is an efficient and well established approach for optimizing the nominal performances of large analog circuits. However, the extension to yield-aware hierarchical methodology, as dictated by the need for safeguarding chip manufacturabllity in scaled technologies, is completely nontrivial. We address two fundamental difficulties in achieving such a methodology: yield-aware pareto performance characterization at the building block level and yield-aware system-level optimization problem formulation. It is shown that our approach is not only able to effectively capture the block performance trade-offs at different yield levels, but also correctly formulate the whole system yield and efficiently perform system-level optimization in presence of process variations. Our approach extends the efficiency of hierarchical analog optimization, enjoyed for improving nominal circuit performances, to yield-aware optimization. Our methodology is demonstrated by the hierarchical optimization of a phased locked loop (PLL) consisting of multiple circuit blocks.

关键词： Analog integrated circuits

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Design and optimization of a digital microfluidic biochip for protein crystallization

Design and optimization of a digital microfluidic biochip fo...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Xu, Tao Chakrabarty, Krishnendu Pamula, Vamsee K. Department of Electrical and Computer Engineering Duke University Durham NC 27708 United States Advanced Liquid Logic Inc. Research Triangle Park NC 27560 United States

ISBN: (纸本)9781424428205

Proteins crystallization is a commonly used technique for protein analysis and subsequent drug design. It predicts the three-dimensional arrangement of the constituent amino acids, which in turn indicates the specific biological function of a protein. Protein crystallization experiments are typically carried out manually on multi-well plates in the laboratory. These experiments are slow, expensive, and error-prone. We present the design of a multi-well plate microfluidic biochip for protein crystallization;this biochip can transfer protein samples, prepare candidate solutions, and carry out crystallization automatically. To reduce the manufacturing cost of such devices, we present an efficient algorithm to generate a pin-assignment plan for the proposed design. The resulting biochip enables control of a large number of on-chip electrodes using only a small number of pins. Based on the pin-constrained chip design, we present an efficient shuttle-passenger-like droplet manipulation method to achieve high-throughput and defect-tolerant well loading.

关键词： Biochips

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PaRS: Fast and near-optimal grid-based cell sizing for library-based design

PaRS: Fast and near-optimal grid-based cell sizing for libra...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Wu, Tai-Hsuan Davoodi, Azadeh Department of Electrical and Computer Engineering University of Wisconsin-Madison 1415 Engineering Dr. Madison WI 53706 United States

ISBN: (纸本)9781424428205

We propose PaSS, a parallel and randomized tool which solves the discrete gate sizing (cell sizing) problem on a grid. PaRS is formulated based on an optimization framework known as Nested Partitions which uses parallelism and randomization from a novel perspective to better identify the optimization direction. It achieves near-optimal solutions for minimizing total power and area subject to meeting a delay constraint. The embarrassingly-parallel nature of PaRS makes it highly efficient. We show small algorithm run-times, in at most minutes for circuits with over 47,000 cells. We make comparison with the optimal solution generated by a custom and parallel branch-and-bound algorithm. Consequently, we are able to generate the optimal solution within hours. While the optimal algorithm uses up to 200 nodes in our grid, PaRS achieves its speedups and near-optimal solutions using only 20 nodes.

关键词： Branch and bound method

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Simultaneous control of power/ground current, wakeup time and transistor overhead in power gated circuits

Simultaneous control of power/ground current, wakeup time an...

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2008 international conference on computer-aided Design, ICCAD

作者： Lee, Yongho Jeong, Deog-Kyoon Kim, Taewhan School of Electrical Engineering and Computer Science Seoul National University Korea Republic of

ISBN: (纸本)9781424428205

Power gating in circuits is one of the effective technologies to allow low leakage and high performance operations. This work aims to analyze and establish the relations between the three important design parameters in power gated circuits: (i) the maximum current flowing from/to power/ground (ii) the wakeup (sleep to active mode transition) time delay and (iii) the number of sleep transistors. With the understanding of relations between the parameters, we propose solutions to the two problems: (1) finding logic clusters and their wakeup schedule to minimize the sleep transistor overhead under the constraints of wakeup time and peak current and (2) finding logic clusters and their wakeup schedule to minimize the wakeup time under the constraints of peak current and the number of sleep transistors. From an experimentation using ISCAS benchmarks, it is shown that our proposed technique is able to explore the search space, finding solutions with 65% - 77% reduced number of sleep transistors and 30% - 36% reduced wakeup time delay, compared to the results by the previous work.

关键词： Time delay

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Clock buffer polarity assignment combined with clock tree generation for power/ground noise minimization

Clock buffer polarity assignment combined with clock tree ge...

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2008 international conference on computer-aided Design, ICCAD

作者： Ryu, Yesin Kim, Taewhan School of Electrical Engineering and Computer Science Seoul National University Korea Republic of

ISBN: (纸本)9781424428205

A new approach to the problem of clock buffer polarity assignment for minimizing power/ground noise on the clock network is presented. The previous approaches solve the assignment problem in two separate steps: (step 1) generating a clock routing tree of minimum total wirelength, satisfying the clock skew constraint and then (step 2) inserting buffering elements with their polarities under the objective of minimizing power/ground noise while satisfying the clock skew constraint. Yet, there is no easy way to predict the result of step 2 during step 1. In our approach, we place the primary importance on the cost of power/ground noise. Consequently, we try to minimize the cost of power/ground noise first and then to construct a clock routing tree later while satisfying the clock skew constraint. Through experimentation using several benchmark circuits, it is shown that this approach is quite effective and produces very good solutions, reducing the power/ground noise by 75 % and the peak current by 26% at the expense of 5% wirelength overhead compared to that produced by the conventional approach.

关键词： Forestry

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Verifying external interrupts of embedded microprocessor in SoC with on-chip bus

Verifying external interrupts of embedded microprocessor in ...

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2008 international conference on computer-aided Design, ICCAD

作者： Yang, Fu-Ching Zhong, Jing-Kun Huang, Ing-Jer Department of Computer Science and Engineering National Sun Yat-sen University Kaohsiung 80424 Taiwan

ISBN: (纸本)9781424428205

The microprocessor verification challenge becomes higher in the on-chip bus (OCB) than in the unit-level. Especially for the external interrupts, since they interface with other IP components, they suffer from the complicated bus protocol and IP conflict problems. This paper proposes a automatic method to verify the microprocessor external interrupt behaviors on the OCB. The verification approach is based on the Processor External Interrupt Verification Tool (PEVT) whose simulation environment is direct-connected memory. In this paper, we implement the PEVT-SoC and successfully verify two SoC platforms, one academic microprocessor and one public domain microprocessor. An interesting bug appears that is impossible to be discovered in the memory bus and not easy to be identified on the OCB. The result shows that the PEVT-SoC effectively shortens the verification time regardless of the system complexity and can be easily migrated to different platforms/microprocessors. With little human effort, even an inexperience designer can generate extensive verification cases in a systematic way.

关键词： System-on-chip

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Thermal-aware reliability analysis for platform FPGAs

Thermal-aware reliability analysis for platform FPGAs

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2008 international conference on computer-aided Design, ICCAD

作者： Mangalagiri, Prasanth Bae, Sungmin Krishnan, Ramakrishnan Xie, Yuan Narayanan, Vijaykrishnan Department of Computer Science and Engineering Pennsylvania State Universiy State College PA 16802 United States

ISBN: (纸本)9781424428205

Increasing levels of integration in Field Programmable Gate Arrays, have resulted in high on-chip power densities, and temperatures. The heterogeneity of components and scaled feature sizes in Platform FPGAs have made them vulnerable to various temperature dependent failure mechanisms. Hence, we need to introduce temperature awareness in tackling such failures that affect the lifetime reliability of FPGAs. In this paper, we present a Dynamic Thermal-aware Reliability Management (DTRM) framework to analyze the impact of temperature variations on the longterm/lifetime reliability of Platform FPGAs. We first study the temperature variations, both across and with-in designs, due to the use of various hard-blocks within a 65nm Platform FPGA. In the presence of such variations, we demonstrate the vulnerability of Platform FPGAs to two different hard-failures, namely, Electromigration, and Time Dependent Dielectric Breakdown (TDDB). We also analyze the performance degradation caused by Negative Bias Temperature Instability (NBTI) in the presence of thermal-variations. We validate the temperature variations estimated by the DTRM framework using a ring oscillator based real-time temperature measurement technique.

关键词： Field programmable gate arrays (FPGA)

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