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Texture filter memory - A power-efficient and scalable texture memory architecture for mobile graphics processors

Texture filter memory - A power-efficient and scalable textu...

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2008 international conference on computer-aided Design, ICCAD

作者： Silpa, B.V.N. Patney, Anjul Krishna, Tushar Panda, Preeti Ranjan Visweswaran, G.S. Department of Computer Science and Engineering Indian Institute of Technology Delhi Hauz Khas New Delhi 110016 India Department of Electrical Engineering Indian Institute of Technology Delhi Hauz Khas New Delhi 110016 India

ISBN: (纸本)9781424428205

With increasing interest in sophisticated graphics capabilities in mobile systems, energy consumption of graphics hardware is becoming a major design concern in addition to the traditional performance enhancement criteria. Among the different steps in the graphics processing pipeline, we have observed that memory accesses during texture mapping - a highly memory intensive phase - contribute 30-40% of the energy consumed in typical embedded graphics processors. This makes the texture mapping subsystem an attractive candidate for energy optimization. We argue that a standard cache hierarchy, commonly used by researchers and commercial graphics processors for texture mapping, is wasteful of energy, and propose the Texture Filter Memory, an energy efficient architecture that exploits locality and the relatively high degree of predictability in texture memory access patterns. Our architecture consumes 75% lesser energy for texturing in a fixed function pipeline, incurring no performance overhead and a small area overhead over conventional texture mapping hardware.

关键词： Memory architecture

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Optimization-based framework for simultaneous circuit-and-system design-space exploration: A high-speed link example

Optimization-based framework for simultaneous circuit-and-sy...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Sredojevic, Ranko Stojanovic, Vladimir Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA 02139 United States

ISBN: (纸本)9781424428205

Connecting system-level performance models with circuit information has been a long-standing problem in analog/mixed-signal front-ends, like radios and high-speed links. High-speed links are particularly hard to analyze because of the complex interplay of device/circuit parasitica and channel filtering operation. In this paper we introduce optimization-based framework for link design-space exploration, connecting the link transmission quality and top-level filter settings with circuit power, sizing and biasing. We derive a special analytical discrete time representation that avoids the size explosion of the symbolic problem description improving the parsing and solver time by orders of magnitude and making this Joint optimization possible in real-time. This robust and accurate problem formulation is derived in signomial form and is compatible with existing optimization approaches to circuit sizing. We demonstrate this optimization framework on a link design-space exploration example, investigating trade-offs between the transmit preemphasis and linear receiver equalizer and their impact on overall link power vs. data rate.

关键词： Economic and social effects

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BSG-route: A length-matching router for general topology

BSG-route: A length-matching router for general topology

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2008 international conference on computer-aided Design, ICCAD

作者： Yan, Tan Wong, Martin D.F. Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign United States

ISBN: (纸本)9781424428205

Length-matching routing is a very important issue for PCB routing. Previous length-matching routers [1]-[3] all have assumptions on the routing topology whereas practical designs may be free of any topological constraint. In this paper, we propose a router that deals with general topology. Unlike previous routers, our router does not impose any restriction on the routing topology. Moreover, our router is gridless. Its performance does not depend on the routing grid size of the input while routers in [1]-[3] do. This is a big advantage because modern PCB routing configurations usually imply huge routing grids. The novelty of this work is that we view the length-matching routing problem as an area assignment problem and use a placement structure, Bounded-Sliceline Grid (BSG) [4], to help solving the problem. Experimental results show that our router can handle practical designs that previous routers can't handle. For designs that they could handle, our router runs much faster. For example, in one of our data, we obtain the result in 88 seconds while the router in [3] takes more than one day.

关键词： Routers

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Temperature aware task sequencing and voltage scaling

Temperature aware task sequencing and voltage scaling

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2008 international conference on computer-aided Design, ICCAD

作者： Jayaseelan, Ramkumar Mitra, Tulika Department of Computer Science National University of Singapore

ISBN: (纸本)9781424428205

On-chip power density and temperature are rising exponentially with decreasing feature sizes. This alarming trend calls for temperature management at every level of system design. In this paper, we propose task sequencing as a powerful and complimentary mechanism to voltage scaling in improving the thermal profile of an embedded system executing a set of periodic heterogenous tasks under timing constraints. We first derive the peak temperature of a repeating task sequence analytically and develop a heuristic to construct the task sequence that minimizes the peak temperature. Experimental evaluation shows that our task sequencing heuristic achieves peak temperature within 0.5C of the optimal solution and 7.47C lower, on an average, compared to the worst sequence for a large range of embedded task sets. We also propose an iterative algorithm that combines task sequencing with voltage scaling to further lower the peak temperature while satisfying the timing constraints. For embedded task sets, our combined task sequencing and voltage scaling approach achieves, on an average, 2.1C-6.94C reduction in peak temperature compared to voltage scaling alone.

关键词： Voltage scaling

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Improving Performance of digest Caches in Network Processors

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15th international conference on High Performance Computing (HiPC 2008)

作者： Chandramohan, Girish Ramaswamy, Govindarajan Akamai Technol India Pvt Ltd Bangalore 560012 Karnataka India Indian Inst Sci Supercomp Educ & Res Ctr Bangalore 560012 Karnataka India

ISBN: (纸本)9783540898931

digest caches have been proposed as an effective method to speed tip packet classification in network processors. In this paper, we show that the presence of a large number of small flows and a few large flows in the Internet has all adverse impact on the performance of these digest caches. In the Internet a few large flows transfer a majority of the packets whereas the contribution of several small flows to the total number of packets transferred is small. In such a scenario, the LRU cache replacement policy, which gives maximum priority to the most recently accessed digest, tends to evict digests belonging to the few large flows. We propose a new cache, management algorithm called Saturating Priority (SP) which aims at improving the performance of digest caches in network processors by exploiting the disparity between the number of flows and the number of packets transferred. Our experimental results demonstrate that SP performs better than the widely used LRU cache replacement policy in size constrained caches. Further, we characterize the misses experienced by flow identifiers, in digest caches.

关键词： Cache memory

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Adjustment-based modeling for statistical static timing analysis with high dimension of variability

Adjustment-based modeling for statistical static timing anal...

引用

2008 international conference on computer-aided Design, ICCAD

作者： Xie, Lin Davoodi, Azadeh Zhang, Jun Wu, Tai-Hsuan Department of Electrical and Computer Engineering University of Wisconsin Madison WI 53706 United States Department of Statistics University of Wisconsin Madison WI 53706 United States

ISBN: (纸本)9781424428205

This paper presents an adjustment-based modeling framework for Statistical Static Timing Analysis (SSTA) when the dimension of parameter variability is high. Instead of building a complex model between the circuit timing and parameter variability, we build a model which adjusts an approximate variation-aware timing into an accurate one. The intuition is that it is simpler to build a model which adjusts an approximate estimate into an accurate one. It is also more efficient to obtain an approximate circuit timing model. The combination of these two observations makes the use of an adjustment-based model a good choice for SSTA with high dimension of parameter variability. To build the adjustment model, we use a simulation-based approach, which is based on Gaussian Process. Combined with intelligent sampling, we show that an adjustment-based model can more effectively capture the nonlinearity of the circuit timing with respect to parameter variability compared to polynomial modeling. We also show that with only 200 samples of the circuit timing and 42 independent parameter variations, adjustmentbased modeling obtains higher accuracy than direct SSTA using quadratic modeling.

关键词： Timing circuits

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Performance estimation and slack matching for pipelined asynchronous architectures with choice

Performance estimation and slack matching for pipelined asyn...

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2008 international conference on computer-aided Design, ICCAD

作者： Gill, Gennette Gupta, Vishal Singh, Montek Dept. of Computer Science Univ. of North Carolina Chapel Hill NC 27599 United States

ISBN: (纸本)9781424428205

This paper presents a fast analytical method for estimating the throughput of pipelined asynchronous systems, and then applies that method to develop a fast solution to the problem of pipelining "slack matching." The approach targets systems with hierarchical topologies, which typically result when high-level (block structured) language specifications are compiled into data-driven circuit implementations. A significant contribution is that our approach is the first to efficiently handle architectures with choice (i.e., the presence of conditional computation constructs such if-then-else and conditional loops). The key idea behind the fast speed of our analysis method is to exploit information about the hierarchy of a given block-structured system, thereby yielding a runtime that is linear in the number of pipeline stages. In contrast, existing approaches typically represent an entire system as a single Petri net or marked graph, and then apply Markov chain analysis or other state enumeration methods with costly runtimes. Building upon our analysis approach, we introduce a novel solution to the problem of slack matching, i.e., determining optimal insertion of FIFO stages into a pipelined design to improve performance. We present both an optimal solution using an MILP formulation, and a fast heuristic algorithm that yielded optimal results for all of our examples.

关键词： Petri nets

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A statistical approach for full-chip gate-oxide reliability analysis

A statistical approach for full-chip gate-oxide reliability ...

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2008 international conference on computer-aided Design, ICCAD

作者： Chopra, Kaviraj Zhuo, Cheng Blaauw, David Sylvester, Dennis Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9781424428205

Gate oxide breakdown is a key factor limiting the useful lifetime of an integrated circuit. Unfortunately, the conventional approach for full chip oxide reliability analysis assumes a uniform oxide-thickness for all devices. In practice, however, gate-oxide thickness varies from die-to-die and vtithin-die and as the precision of process control worsens an alternative reliability analysis approach is needed. In this work, we propose a statistical framework for chip level gate oxide reliability analysis while considering both die-to-die and vtithin-die components of thickness variation. The thickness of each device is modeled as a distinct random variable and thus the full chip reliability estimation problem is defined on a huge sample space of several million devices. We observe that the full chip oxide reliability is independent of the relative location of the individual devices. This enables us to transform the problem such that the resulting representation can be expressed in terms of only two distinct random variables. Using this transformation we present a computationally efficient and accurate approach for estimating the full chip reliability while considering spatial correlations of gate-oxide thickness. We show that, compared to Monte Carlo simulation, the proposed method incurs an error of only 1-6% while improving the runtime by around three orders.

关键词： Reliability analysis

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MC-sim: An efficient simulation tool for MPSoC designs

MC-sim: An efficient simulation tool for MPSoC designs

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2008 international conference on computer-aided Design, ICCAD

作者： Cong, Jason Gururaj, Karthik Han, Guoling Kaplan, Adam Naik, Mishali Reinman, Glenn Computer Science Department University of California Los Angeles Los Angeles CA 90095 United States

ISBN: (纸本)9781424428205

The ability to integrate diverse components such as processor cores, memories, custom hardware blocks and complex network-on-chip (NoC) communication frameworks onto a single chip has greatly increased the design space available for system-on-chip (SoC) designers. Efficient and accurate performance estimation tools are needed to assist the designer in making design decisions. In this paper, we present MC-Sim, a heterogeneous multi-core simulator framework which is capable of accurately simulating a variety of processor, memory, NoC configurations and application specific coprocessors. We also describe a methodology to automatically generate fast, cycletrue behavioral, C-based simulators for coprocessors using a high-level synthesis tool and integrate them with MC-Sim, thus augmenting it with the capacity to simulate coprocessors. Our C-based simulators provide on an average 45x improvement in simulation speed over that of RTL descriptions. We have used this framework to simulate a number of real-life applications such as the MPEG4 decoder and litho-simulation, and experimented with a number of design choices. Our simulator framework is able to accurately model the performance of these applications (only 7% off the actual implementation) and allows us to explore the design space rapidly and achieve interesting design implementations.

关键词： Simulators

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A polynomial time approximation scheme for timing constrained minimum cost layer assignment

A polynomial time approximation scheme for timing constraine...

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2008 international conference on computer-aided Design, ICCAD

作者： Hu, Shiyan Li, Zhuo Alpert, Charles J. Dept. of Electrical and Computer Engineering Michigan Technological University Houghton MI 49931 United States IBM Austin Research Laboratory 11501 Burnet Road Austin TX 78758 United States

ISBN: (纸本)9781424428205

As VLSI technology enters the nanoscale regime, interconnect delay becomes the bottleneck of circuit performance. Compared to gate delays, wires are becoming Increasingly resistive which makes it more difficult to propagate signals across the chip. However, more advanced technologies (65nm and 45nm) provide relief as the number of metal layers continues to increase. The wires on the upper metal layers are much less resistive and can be used to drive further and faster than on thin metals. This provides an entirely new dimension to the traditional wire sizing problem, namely, layer assignment for efficient timing closure. Assigning all wires to thick metals improves timing, however, mutability of the design may be hurt. The challenge is to assign minimal amount of wires to thick metals to meet timing constraints. In this paper, the minimum cost layer assignment problem is proven to be NP-Complete. As a theoretical solution for NP-complete problems, a polynomial time approximation scheme is proposed. The new algorithm can approximate the optimal layer assignment solution by a factor of 1 + Ε In O(m log log m · n 3/Ε2) time for O

关键词： Wire

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