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Electrically driven optical proximity correction based on linear programming

Electrically driven optical proximity correction based on li...

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2008 international conference on computer-aided Design, ICCAD

作者： Banerjee, Shayak Elakkumanan, Praveen Liebmann, Lars W. Orshansky, Michael Department of Electrical and Computer Engineering University of Texas Austin TX United States IBM Corp. Hopewell Junction NY United States

ISBN: (纸本)9781424428205

Conventional optical proximity correction (OPC) tools aim to minimize edge placement errors (EPE) due to the optical and resist process by moving mask edges. However, in low-kl lithography, especially at 45nm and beyond, printing perfect polygons is practically impossible to achieve. In addition, prohibitively high mask complexity is incurred, leading to high mask cost. Given the impossibility of perfect printing, we argue that aiming to reduce the error of electrical discrepancy between the ideal and the printed contours is a more reasonable strategy. In fact, we show that contours with non-minimal EPE may result in closer match to the desired electrical performance. Towards achieving this objective, we developed a new electrically driven OPC (ED-OPC) algorithm. The tool combines lithography simulation with accurate electrical modeling of resist contours to predict the on/off current through a transistor gate. The computation of mask edge movements is cast as a linear program based on optical and electrical sensitivities. The objective is to minimize the error in saturation current between printed and target shapes. This optimization is then solved with fast runtime. The results on industrial 45nm SOI layouts using high-NA immersion lithography models show up to a 5% improvement in accuracy of timing over conventional OPC. This is achieved at less than 26% runtime overheads, while also lowering mask complexity by up to 43%. The results confirm that better timing accuracy can be achieved despite larger edge placement error.

关键词： Errors

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Statistical modeling of metal-gate work-function variability in emerging device technologies and implications for circuit design

Statistical modeling of metal-gate work-function variability...

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2008 international conference on computer-aided Design, ICCAD

作者： Dadgour, Hamed De, Vivek Banerjee, Kaustav Department of Electrical and Computer Engineering University of California Santa Barbara CA 93106 United States Circuit Research Lab. Intel Corporation Hillsboro OR 97124 United States

ISBN: (纸本)9781424428205

For the first time, a new source of random threshold voltage (V th) fluctuation in emerging metal-gate transistors is identified, analytically modeled and investigated for its device and circuit-level implications. The new source of variability, christened Work-Function Variation (WFV), is caused by the dependency of metal work-function on the orientation of its grains. A statistical framework is developed, which enables estimation of the key parameters of work-function distribution by identifying the physical dimensions of the devices and properties of materials used in the fabrication. This paper offers three major contributions for process, device and circuit designers. First, the proposed model can be employed to identify suitable materials and fabrication processes that can reduce the impact of Vth fluctuation due to WFV. For instance, four types of metal nitride gate materials (TiN and TaN for NMOS and WN and MoN for PMOS devices) are studied and it is shown that TiN and WN result in lower Vth fluctuation. Second, device engineers can benefit from the result of this work by evaluating the WFV level of various types of classical or non-classical metal-gate CMOS transistors. As an example, it is shown that FinFET transistors are less affected by WFV compared to FD-SOI and Bulk-Si devices due to their larger gate area. Third, circuit designers can utilize this model to investigate the impact of such a variation on the key performance and reliability parameters of the circuits. For instance, an SRAM cell is analyzed in the presence of V th fluctuations due to WFV and it is shown that such variations can result in considerable performance and reliability degradation.

关键词： Work function

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MUTE-AES: A multiprocessor architecture to prevent power analysis based side channel attack of the AES algorithm

MUTE-AES: A multiprocessor architecture to prevent power ana...

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2008 international conference on computer-aided Design, ICCAD

作者： Ambrose, Jude Angelo Parameswaran, Sri Ignjatovic, Aleksandar School of Computer Science and Engineering University of New South Wales Sydney Australia

ISBN: (纸本)9781424428205

Side channel attack based upon the analysis of power traces is an effective way of obtaining the encryption key from secure processors. Power traces can be used to detect bitflips which betray the secure key. Balancing the bitflips with opposite bitflips have been proposed, by the use of opposite logic. This is an expensive solution, where the balancing processor continues to balance even when encryption is not carried out in the processor. We propose, for the first time, a multiprocessor algorithmic balancing technique to prevent power analysis of a processor executing an AES cryptographic program, a popular encryption standard for embedded systems. Our technique uses a dual processor architecture where two processors execute the same program in parallel, but with complementary intermediate data, thus balancing the bitflips. The second processor works in conjunction with the first processor for balancing only when the AES encryption is performed, and both processors carry out independent tasks when no encryption is being performed. Accessing the encryption key or the input data by the first processor begins the obfuscation by the second processor. To stop the encryption by the second processor, we use a novel signature detection technique, which detects the end of the encryption automatically. The multiprocessor balancing approach (MUTE-AES) proposed here reduces performance by 0.42% and increases the size of the hardware by 2 (though reduces to 0.1% when no encryption is being performed). We show that Differential Power Analysis (DPA) fails when our technique is applied to AES. We further illustrate, that by the use of this balancing strategy, the adversary is left with noise from the power profile with little useful information.

关键词： Side channel attack

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High Performance Computing - HiPC 2008 - 15th international conference, Proceedings

High Performance Computing - HiPC 2008 - 15th International ...

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15th international conference on High Performance Computing, HiPC 2008

ISBN: (纸本)354089893X

The proceedings contain 46 papers. The topics discussed include: extreme computing on the distributed European infrastructure for supercomputing applications - DEISA;towards networked computers: what can be learned from distributed computing;computational environments for coupling multiphase flow, transport, and mechanics in porous media;the excitement in parallel computing;improving performance of digest caches in network processors;optimization of BLAS on the cell processor;fine tuning matrix multiplications on multicore;the design and architecture of MAQAOAdvisor: a live tuning guide;a load balancing framework for clustered storage systems;construction and evaluation of coordinated performance skeletons;data sharing analysis of emerging parallel media mining;efficient PDM sorting algorithms;accelerating cone beam reconstruction using the CUDA-enabled GPU;and improving the performance of tensor matrix vector multiplication in cumulative reaction probability based quantum chemistry codes.

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Hybridization of K-Means and Harmony Search Methods for Web Page Clustering

Hybridization of K-Means and Harmony Search Methods for Web ...

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ieee WIC acm international conference on Web Intelligence (WI)

作者： Rana Forsati MohammadReza Meybodi Mehrdad Mahdavi AzadehGhari Neiat Department of Computer Engineering Islamic Azad University Qazvin Iran Department of Computer Engineering Amirkabir University of Technology슠 Tehran Iran Department of Computer Engineering Sharif University of Technology Tehran Iran Department of Computer Engineering Islamic Azad University Tehran Iran

Clustering is currently one of the most crucial techniques for dealing with massive amount of heterogeneous information on the web, which is beyond human beingpsilas capacity to digest. Recent studies have shown that the most commonly used partitioning-based clustering algorithm, the K-means algorithm, is more suitable for large datasets. However, the K-means algorithm can generate a local optimal solution. In this paper we present novel harmony search clustering algorithms that deal with documents clustering based on harmony search optimization method. By modeling clustering as an optimization problem, first, we propose a pure harmony search based clustering algorithm that finds near global optimal clusters within a reasonable time. Contrary to the localized searching of the K-means algorithm, the harmony search clustering algorithm performs a globalized search in the entire solution space. Then harmony clustering is integrated with the K-means algorithm in three ways to achieve better clustering. The proposed algorithms improve the K-means algorithm by making it less dependent on the initial parameters such as randomly chosen initial cluster centers, hence more stable. In the experiments we conducted, we applied the proposed algorithms, K-means clustering algorithm on five different document datasets. Experimental results reveal that the proposed algorithms can find better clusters when compared to K-means and the quality of clusters is comparable and converge to the best known optimum faster than it.

关键词： Search methods Web pages Clustering algorithms Partitioning algorithms Optimization methods Clustering methods Intelligent agent Information retrieval Data mining Stochastic processes

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High-performance routing at the nanometer scale

High-performance routing at the nanometer scale

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ieee/acm international conference on computer-aided Design

作者： Roy, Jaffod A. Markov, Igor L. Univ Michigan Dept EECS Ann Arbor MI 48109 USA

ISBN: (纸本)9781424413812

In this work we describe significant improvements to core routing technologies and outperform the best results from the ISPD '07 Global Routing Contest, as well as previous literature, in terms of route completion, runtime and total wirelength. In particular, our router, FGR, improves upon wirelengths produced by BoxRouter and MaizeRouter in March 2007 by 9.9% and 8.4%, respectively. Additionally, we reveal the mathematical basis of negotiated-congestion routing, offer comprehensive analysis of existing routing techniques and discuss several applications at the nanometer scale.

关键词： computer aided design

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Fast exact Toffoli network synthesis of reversible logic

Fast exact Toffoli network synthesis of reversible logic

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ieee/acm international conference on computer-aided Design

作者： Wille, Robert Grosse, Daniel Univ Bremen Grp Comp Architecture D-28359 Bremen Germany

ISBN: (纸本)9781424413812

The research in the field of reversible logic is motivated by its application in low-power design, optical computing and quantum computing. Hence synthesis of reversible logic has become a very important research area in the last years. In this paper exact algorithms for the synthesis of generalized Toffoli networks are considered. We present an improvement of an existing synthesis approach that is based on Boolean Satisfiability. Furthermore, the principle limits of the original and the improved approach are shown. Then, we propose a new method using problem specific knowledge during the synthesis process to overcome these limits. Experimental results demonstrate improvements of the overall synthesis time up to four orders of magnitude.

关键词： computer circuits

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Incremental learning approach and SAT model for boolean matching with don't cares

Incremental learning approach and SAT model for boolean matc...

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ieee/acm international conference on computer-aided Design

作者： Wang, Kuo-Hua Chan, Chung-Ming Fu Jen Catholic Univ Dept Comp Sci & Informat Engn Hsinchuang City 24205 Taipei County Taiwan

ISBN: (纸本)9781424413812

In this paper, we will propose an incremental learning approach to solve Boolean matching for incompletely specified functions. This approach can incrementally analyze current feasible partial mappings, detect and eliminate redundant manipulations in a proactive way. A new type of signature exploiting single variable symmetries is also given to reduce the searching space. Moreover, a SAT model of Boolean matching will be proposed to handle large Boolean functions. Through the utilization of these novel mechanisms, a drastic improvement on the performance of our Boolean matching algorithms are achieved. The experimental results demonstrate the effectiveness and efficiency of the proposed learning-based and SAT-based Boolean matching algorithms on many large benchmarking circuits.

关键词： computer aided design

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Inductive equivalence checking under retiming and resynthesis

Inductive equivalence checking under retiming and resynthesi...

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ieee/acm international conference on computer-aided Design

作者： Jiang, Jie-Hong R. Hung, Wei-Lun Natl Taiwan Univ Dept Elect Engn Grad Inst Elect Engn Taipei 10617 Taiwan

ISBN: (纸本)9781424413812

Retiming and resynthesis are among the most important techniques for practical sequential circuit optimization. However, their applicability is much limited due to verification concerns. Overcoming the verification bottleneck is a supreme task. This paper studies both the theoretical and practical aspects of inductive verification on the equivalence between circuits under retiming and resynthesis transformation. We study the completeness condition of the inductive approach to equivalence checking and show that prior work is only complete for circuits transformed under retiming or resynthesis, but not both. We overcome prior limitation and make complete the equivalence checking for circuits transformed up to retiming+resynthesis+retiming. The theoretical insights lead to a robust satisfiability formulation of verification under various retiming and resynthesis scenarios. Experimental results demonstrate the scalability of the approach. Several previously unverifiable circuits and unverifiable transformation scenarios can now be verified effectively.

关键词： computer aided design

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Timing budgeting under arbitrary process variations

Timing budgeting under arbitrary process variations

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ieee/acm international conference on computer-aided Design

作者： Chen, Ruiming Zhou, Hai NuCAD Electrical Engineering and Computer Science Northwestern University

ISBN: (纸本)9781424413812

Timing budgeting under process variations is an important step in a statistical optimization flow. We propose a novel formulation of the problem where budgets are statistical instead of deterministic as in existing works. This new formulation considers the changes of both the means and variances of delays, and thus can reduce the timing violation introduced by ignoring the changes of variances. We transform the problem to a linear programming problem using a robust optimization technique. Our approach can be used in late-stage design where the detailed distribution information is known, and is most useful in early-stage design since our approach does not assume specific underlying distributions. In addition, with the help of block-level timing budgeting, our approach can reduce the timing pessimism. Our approach is applied to the leakage power minimization problem. The results demonstrate that our approach can reduce timing violation from 690ps to 0ps, and the worst total leakage power by 17.50% on average.

关键词： Budget control

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