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Checking equivalence of quantum circuits and states

Checking equivalence of quantum circuits and states

引用

ieee/acm international conference on computer-aided Design

作者： Viamontes, George R. Markov, Igor L. Hayes, John P. Lockheed Martin ATL 3 Execut Campus Cherry Hill NJ 08002 USA Univ Michigan Adv Comp Architeture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)9781424413812

Among the post-CMOS technologies currently under investigation, quantum computing (QC) holds a special place. QC offers not only extremely small size and low power, but also exponential speed-ups for important simulation and optimization problems. It also poses new CAD problems that are similar to, but more challenging, than the related problems in classical (non-quantum) CAD, such as determining if two states or circuits are functionally equivalent. While differences in classical states are easy to detect, quantum states, which are represented by complex-valued vectors, exhibit subtle differences leading to several notions of equivalence. This provides flexibility in optimizing quantum circuits, but leads to difficult new equivalence-checking issues for simulation and synthesis. We identify several different equivalence-checking problems and present algorithms for practical benchmarks, including quantum communication and search circuits, which are shown to be very fast and robust for hundreds of qubits.

关键词： computer aided design

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The FAST methodology for high-speed SoC/computer simulation

The FAST methodology for high-speed SoC/computer simulation

引用

ieee/acm international conference on computer-aided Design

作者： Chiou, Derek Sunwoo, Dam Kim, Joonsoo Patil, Nikhil Reinhart, William H. Johnson, D. Eric Xu, Zheng Univ Texas Austin Austin TX 78712 USA

ISBN: (纸本)9781424413812

This paper describes the FAST methodology that enables a single FPGA to accelerate the performance of cycle-accurate computer system simulators modeling modern, realistic SoCs, embedded systems and standard desktop/laptop/server computer systems. The methodology partitions a simulator into (i) a functional model that simulates the functionality of the computer system and (ii) a predictive model that predicts performance and other metrics. The partitioning is crafted to map most of the parallel work onto a hardware-based predictive model, eliminating much of the complexity and difficulty of simulating parallel constructs on a sequential platform. FAST conventions and libraries have been designed to make creating, modifying, using and measuring such simulators straightforward. We describe a prototype FAST system: a full-system, RTL-level cycle-accurate-capable computer system simulator that executes the x86 ISA, boots unmodified Linux and executes unmodified x86 applications. The prototype runs two to three orders of magnitude faster than the fastest Intel and AMD RTL-level cycle-accurate x86 software-based simulators and about six to seven times faster than RTL simulation.

关键词： Simulators

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Enhancing design robustness with reliability-aware resynthesis and logic simulation

Enhancing design robustness with reliability-aware resynthes...

引用

ieee/acm international conference on computer-aided Design

作者： Krishnaswamy, Smita Plaza, Stephen M. Markov, Igor L. Hayes, John P. Univ Michigan Adv Comp Architecture Lab Ann Arbor MI 48109 USA

ISBN: (纸本)9781424413812

While circuit density and power efficiency increase with each major advance in IC technology, reliability with respect to soft errors tends to decrease. Current solutions to this problem such as TMR require high area and power overhead. In this work soft-error reliability is improved with minimal area overhead by careful, localized circuit restructuring. The key idea is to increase logic masking of errors by taking advantage of conditions already present in the circuit, such as observability don't-cares. We describe two circuit modification techniques to improve reliability: don't-care-based resynthesis and local rewriting. A key feature of these techniques is fast, on-the-fly estimation of soft error rate (SER) using our reliability evaluator AnSER. This tool is compared against prior SER evaluators and found to run orders of magnitude faster We show empirically that our reliability-driven synthesis methods can reduce SER by 29-40% with only 5-13% area overhead

关键词： computer circuits

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A performance-driven QBF-Based iterative logic array representation with applications to verification, debug and test

A performance-driven QBF-Based iterative logic array represe...

引用

ieee/acm international conference on computer-aided Design

作者： Mangassarian, Hratch Veneris, Andreas Safarpour, Sean Benedetti, Marco Smith, Duncan Univ Toronto ECE Dept Toronto ON M5S 3G4 Canada Univ Toronto Dept CS Toronto ON M5S 3G4 Canada Univ Orleans LIFO F-45067 Orleans France

ISBN: (纸本)9781424413812

Many CAD for VLSI techniques use time-frame expansion, also known as the Iterative Logic Array representation, to model the sequential behavior of a system. Replicating industrialsize designs for many time-frames may impose impractically excessive memory requirements. This work proposes a performance-driven, succinct and parametrizable Quantified Boolean Formula (QBF) satisfiability encoding and its hardware implementation for modeling sequential circuit behavior. This encoding is then applied to three notable CAD problems, namely Bounded Model Checking (BMC), sequential test generation and design debugging. Extensive experiments on industrial circuits confirm outstanding run-time and memory gains compared to state-of-the-art techniques, promoting the use of QBF in CAD for VLSI.

关键词： computer aided design

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2007 ieee/acm international conference on computer-aided Design, ICCAD

2007 IEEE/ACM International Conference on Computer-Aided Des...

引用

2007 ieee/acm international conference on computer-aided Design, ICCAD

ISBN: (纸本)1424413826

The proceedings contain 142 papers. The topics discussed include: a fast and high-capacity electromagnetic solution for high-speed IC design;impedance extraction for 3-D structures with multiple dielectrics using preconditioned boundary element method;statistical analysis of RF circuits using combined circuit simulator-full wave field solver approach;slot allocation using logical networks for TDM virtual-circuit configuration for network-on-chip;real-time adaptive on-chip communication scheme;using functional independence conditions to optimize the performance latency-insensitive systems;a geometric approach for early power grid verification using current constraints;stochastic extended Krylov subspace method for variational analysis of on-chip power grid networks;and parallel domain decomposition for simulation of large-scale power grids.

关键词： Electric power transmission networks

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Bounding L2 gain system error generated by approximations of the nonlinear vector field

Bounding L2 gain system error generated by approximations of...

引用

2007 ieee/acm international conference on computer-aided Design, ICCAD

作者： Kin, Cheong Sou Megretski, Alexandre Daniel, Luca Department of Electrical Engineering and Computer Science Massachusetts Institute of Technology Cambridge MA 02139 United States

ISBN: (纸本)1424413826

Typical nonlinear model order reduction approaches need to address two issues: reducing the order of the model, and approximating the vector field. In this paper we focus exclusively on the second issue, and present results characterizing the repercussions at the system level of vector field approximations. The error assessment problem is formulated as the L2 gain upper bounding problem of a scaled feedback interconnection. Applying the small gain theorem in the proposed setup, we prove that the L2 gain of the error system is upper bounded by the L2 gain of the vector field approximation error, provided it is small. In addition, the paper also presents a numerical procedure, based on the IQC/LMI approach, to perform the error estimation task with less conservatism. A numerical example is given in this paper to demonstrate the practical implications of the presented results. © 2007 ieee.

关键词： Errors

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Finding linear building-blocks for RTL synthesis of polynomial datapaths with fixed-size bit-vectors

Finding linear building-blocks for RTL synthesis of polynomi...

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2007 ieee/acm international conference on computer-aided Design, ICCAD

作者： Gopalakrishnan, Sivaram Kalla, Priyank Brandon Meredith, M. Enescu, Florian Electrical and Computer Engineering University of Utah Salt Lake City UT 84112 United States Mathematics and Statistics Georgia State University Atlanta GA 30303 United States

ISBN: (纸本)1424413826

Polynomial computations over fixed-size bit-vectors are found in many practical datapath designs. For efficient RTL synthesis, it is important to identify good decompositions of the polynomial into smaller/simpler units. Symbolic computer algebra algorithms and tools have been used for this purpose. However, fixed-size (m) bit-vector arithmetic is polynomial algebra over the finite integer ring Z2m, which is a non-unique factorization domain (non-UFD). While non-UFDs provide an extra freedom to search for decompositions, they complicate polynomial manipulation as traditional division-based algorithms are inapplicable. This paper presents new mathematical concepts for polynomial decomposition over Z2m for RTL synthesis over fixed-size m-bit vectors. Given a polynomial, we identify a specific set of linear expressions and compute the Gröbner bases of their ideal (over non-UFD Z2m) using syzygies. This basis serves as good building-blocks for the given computation. A decomposition is identified by subsequent Gröbner basis reduction. Experimental results demonstrate significant area savings due to our approach, as compared against contemporary datapath synthesis techniques. © 2007 ieee.

关键词： Polynomials

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Archer: A history-driven global routing algorithm

Archer: A history-driven global routing algorithm

引用

2007 ieee/acm international conference on computer-aided Design, ICCAD

作者： Ozdal, Muhammet Mustafa Wong, Martin D. F. Intel Corporation Hillsboro OR 97124 United States Dept. of Electrical and Computer Engineering Univ. of Illinois at Urbana-Champaign Urbana IL 61801 United States

ISBN: (纸本)1424413826

Global routing is an important step in the physical design process. In this paper, we propose a new global routing algorithm. Archer, which resolves some of the most common problems with the stateof-the-art global routers. It is known that concurrent global routing algorithms are typically too expensive to be applied on today's large designs, which may contain up to a million nets. On the other hand, iterative rip-up and reroute (RNR) based algorithms are susceptible to getting stuck in local optimal solutions. In this paper, we propose an RNR-based global routing algorithm, that guides the routing iterations out of local optima through effective usage of congestion histories. We also focus on the problem of how to enable a smooth trade-off between seemingly conflicting objectives of overflow and wirelength minimization. Furthermore, we propose a Lagrangian relaxation based bounded-length min-cost topology improvement algorithm that enables Steiner trees to change dynamically for the purpose of congestion optimization. Our experiments show that Archer obtains congestion-free solutions for all circuits in the standard ISP.D98 benchmarks, which is the best result published so far. Furthermore, it produces better results than the best results reported in the ISPD-07 Global Routing Contest in terms of routability. Compared to FastRoute [18, 19], which is the stateof-the-art RNR-based global routing algorithm, Archer improves routability by 30%, and reduces the wirelengths by 32% on the average on. ISPD07 benchmarks. © 2007 ieee.

关键词： Routing algorithms

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Design automation for analog: The next generation of tool challenges

Design automation for analog: The next generation of tool ch...

引用

ieee/acm international conference on computer aide digest

作者： Rutenbar, Rob A. Carnegie Mellon Univ Dept Elect & Comp Engn Pittsburgh PA 15213 USA

ISBN: (纸本)9781595933898

The decade of the 1990s saw the first wave of practical "post-SPICE" tools for analog designs. A range of synthesis, optimization, layout and modeling techniques made their way from academic prototypes to first-generation commercial offerings. We offer some pragmatic prognostications for what the next wave might (or, more bluntly, should) focus on next as pressure to improve AMS design productivity grows.

关键词： analog mixed-signal integrated circuits computer-aided design

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Near-term industrial perspective of analog CAD

Near-term industrial perspective of analog CAD

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ieee/acm international conference on computer aide digest

作者： Labrecque, Christopher Synopsys Inc Mountain View CA 94004 USA

ISBN: (纸本)9781595933898

Analog and mixed-signal CAD looks like a nice success story: there's been significant research in building design automation tools since the late 80's, and commercial tools have been on the market for several years now. However, the majority of AMS (Analog/Mixed-Signal) designers still use manual design only, focused around the SPICE simulator. So why are designers not or slowly adopting these CAD tools? This paper will present a reality check on the current state of the art of AMS design tools for industrial usage.

关键词： analog mixed-signal integrated circuits computer-aided design

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