Yield and variability are becoming detractors for successful design in sub-90-nm process technologies. We consider the fundamental lithography and process issues that are driving variability and yield and the role of ...
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ISBN:
(纸本)9781595933898
Yield and variability are becoming detractors for successful design in sub-90-nm process technologies. We consider the fundamental lithography and process issues that are driving variability and yield and the role of design rules in future processes. We examine the importance of layout-aware modeling and layout regularity, including advantages and cost. Characterization structures for examining the electrical effects of device-level variability are discussed as well as circuit techniques for mitigating variability and yield challenges.
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pipelined rings that can operate on multi...
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ISBN:
(纸本)9781595933898
We present a technique for increasing the throughput of stream processing architectures by removing the bottlenecks caused by loop structures. We implement loops as self-timed pipelined rings that can operate on multiple data sets concurrently. Our contribution includes a transformation algorithm which takes as input a high-level program and gives as output the structure of an optimized pipeline ring. Our technique handles nested loops and is further enhanced by loop unrolling. Simulations run on benchmark examples show a 1.3 to 4.9x speedup without unrolling and a 2.6 to 9.7x speedup with twofold loop unrolling.
This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep submicron point-to-point interconnects. The proposed model accurately predicts the delay i...
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ISBN:
(纸本)9781595933898
This work introduces an extended linear pattern-dependent model for high-level signal delay estimation in high-speed very deep submicron point-to-point interconnects. The proposed model accurately predicts the delay in both inductively and capacitively coupled lines for the complete set of the switching patterns and not only for capacitively coupled lines or worst-case T, lay as in previous works. We also consider process variations in the formulation of the model and propose a moment-based approach for the inclusion of variations. The accuracy of the model has been assessed by means of extensive experiments. Moreover, we show how the model can be applied at high levels of abstraction in order to explore coding-based alternatives to improve throughput.
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design complexities, tightening time-to-market co...
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ISBN:
(纸本)9781595933898
The use of CMOS nanometer technologies at 65 nm and below will pose serious challenges on the design of mixed-signal integrated systems in the very near future. Rising design complexities, tightening time-to-market constraints, leakage power, increasing technology tolerances, and reducing supply voltages are key challenges that designers face. Novel types of devices, new process materials and new reliability issues are next on the horizon. We discuss new design methodologies and EDA tools that are being or need to be developed to address the problems of designing such mixed-signal integrated systems.
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward way is to structurally map the gates in...
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ISBN:
(纸本)9781595933898
Designing asynchronous circuits by reusing existing synchronous tools has become a promising solution to the problem of poor CAD support in asynchronous world. A straightforward way is to structurally map the gates in a synchronous netlist to their functionally equivalent modules which use delay-insensitive codes. Different trade-offs exist in previous methods between the overheads of the implementations and their robustness. The aim of this paper is to optimise the area of asynchronous circuits using partial acknowledgement concept. We employ this concept in two design flows, which are implemented in a software tool to evaluate the efficiency of the method. The benchmark results show the average reduction in area by 28% and in the number of inter-functional module wires that require timing verification by 67%, compared to NCL-X.
This paper presents figures of merit and error formulae to determine which interconnects require volume discretization in the GHZ range. Most of the previous work focused mainly on efficient modeling of volume discret...
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ISBN:
(纸本)9781595933898
This paper presents figures of merit and error formulae to determine which interconnects require volume discretization in the GHZ range. Most of the previous work focused mainly on efficient modeling of volume discretized interconnects using several integration and reduction techniques. However, little work has been done to characterize when using the simple DC model has an impact on critical circuit metrics such as delay, impedance ...etc. Most of the previous work simply assumes that when skin depth becomes smaller than the wire cross section dimensions, volume discretization becomes essential. However, careful analysis in this paper shows that this assumption is invalid and a figure of merit is derived to characterize when volume discretization of single and coupled wires is required. This derived figure of merit is shown to depend solely on the interconnect dimensions and spacing and is independent of the type of the materials used or technology scaling.
Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modem IC design. In this paper we develop a novel methodology for power grid verification which is base...
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ISBN:
(纸本)9781595933898
Identifying worst-case voltage drop conditions in every module supplied by the power grid is a crucial problem in modem IC design. In this paper we develop a novel methodology for power grid verification which is based on accurately constructing the space of current variations of the supplied modules and locating its precise points that yield the worst-case voltage drop conditions. The construction of the current space is performed via plain simulation and statistical extrapolation using results from extreme value theory. The method overcomes limitations of past methods which either relied on loosely bounding the worst-case voltage drop, or abstracted the current space in a vague and incomplete set of bound-type constraints. Experimental results verify the potential of the proposed method to identify worst-case conditions and demonstrate the pessimism inherent in previous bound-type approaches.
Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an ...
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ISBN:
(纸本)9781595933898
Power/ground noise is a major source of VLSI circuit timing variations. This work aims to reduce clock network induced power noise by assigning different signal polarities (opposite switchings) to clock buffers in an existing buffered clock tree. Three assigmnent algorithms are proposed: (1) partitioning, (2) 2-coloring on minimum spanning tree and (3) recursive min-matching. A post-processing of clock buffer sizing is performed to achieve desired clock skew. SPICE based experimental results indicate that our techniques could reduce the average peak current and average delay variations by 44% and 54% respectively.
This paper examines how circuits and systems made from molecular QCA devices might function. Our design constraints are "chemically reasonable" in that we consider the characteristics and dim ensions of devi...
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ISBN:
(纸本)9781595933898
This paper examines how circuits and systems made from molecular QCA devices might function. Our design constraints are "chemically reasonable" in that we consider the characteristics and dim ensions of devices and sca oldings (circuit boards to attach devices to) that have actually been fabricated (currently in isolation). We will show that not only is the work presented here a necessary first step for any work in QCA CAD, but also that by considering issues related to design can actually help shape experiments in the physical sciences for an emerging, nano-scale devices. Our work shows that circuits, sca oldings, substrates, and devices must all be considered sinultaneously. Otherwise, there is a very real possibility that the devices and sca oldings that are eventually manufactured will result in devices that only work in isolation. This work is especially timely as experimentalists are currently working to merge the different experimental tracks - ie. to selectively place a QCA device.
Reliable prediction of parametric yield for a specific design is difficult;a significant reason is the reliance of the yield estimation methods on the hard-to-measure distributional properties of the process data. Exi...
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ISBN:
(纸本)9781595933898
Reliable prediction of parametric yield for a specific design is difficult;a significant reason is the reliance of the yield estimation methods on the hard-to-measure distributional properties of the process data. Existing methods are inadequate when dealing with real-life distributions of process and environmental parameters, and limited availability of parameter data during early design. This paper proposes a robust technique for full-chip parametric yield estimation;the proposed work is based on the rigorous notions of non-parametric robust statistics which permits estimation based on the knowledge of the range and the limited number of moments (e.g. mean and variance) of the parameter distributions. Fully or partially specified process and environmental parameters can be described by robust representations, and used to estimate probabilistic bounds for leakage dissipation. The proposed approach is applied to estimating the chip-level parametric yield. The experimental results show that the robust estimation algorithm improves the total leakage estimate by 5-13% at the 99(th) percentile across distinct frequency bins, compared to using only the intervals of partially-specified parameters.
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