As part of integrated circuit design verification, one should check if the voltage drop on the power grid exceeds some critical threshold. One way to do this is by simulation, but that is computationally expensive and...
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ISBN:
(纸本)9781595933898
As part of integrated circuit design verification, one should check if the voltage drop on the power grid exceeds some critical threshold. One way to do this is by simulation, but that is computationally expensive and gets prohibitive for large circuits with a large variety of possible operational modes. Another limitation of a simulation-based approach is that it requires complete knowledge of the logic circuitry drawing current from the grid, thus precluding grid verification early in the design process. In this paper, we model the grid as an RLC circuit and we propose three verification techniques that can be applied in the early stages of the design process. These techniques do not require exact knowledge of the circuit currents. Instead, the currents drawn by the logic beneath the power grid are described by means of current constraints that capture the uncertainty about circuit details and activity. The first verification approach gives the exact worst-case voltage drop at every node of the grid, but it is slow. A, second faster approach gives conservative bounds on the worst-case voltage drop at every node of the grid. The third approach is much faster;it is a conservative approach which simply checks if the grid voltage drop exceeds some pre-defined thresholds without actually computing the worst-case voltage drop at every node.
We present global routing optimization methods which are not based on rip-up and re-route framework. In particular, the routing optimization is based on trunk decomposition [13] of the global routing. In this framewor...
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ISBN:
(纸本)9781595933898
We present global routing optimization methods which are not based on rip-up and re-route framework. In particular, the routing optimization is based on trunk decomposition [13] of the global routing. In this framework, the route of a net is decomposed into sets of wiring segments. By viewing a wiring segment as an "atomic object" of perturbation, we can efficiently evaluate the effect of routing tree perturbation. We propose two complementary routing optimization methods, namely segment partitioning and segment migration. These targeted optimizers can improve congestion related routing objectives by quickly shuffling wiring segments across different routing channels. Our routing approach produces better results compared to rip,-up and re-route method based router Labyrinth [14] with average total overflow reduction of more than 88% while taking only 61% of runtime required by ripup and reroute phase of Labyrinth. When applied to the output of Labyrinth, the approach, on average, reduces the total overflow by more than 97% with complete overflow elimination for four circuits, while requiring additional runtime of just 33%. On a larger benchmark suite, the total overflow reduction of more than 86% is obtained, with complete overflow elimination for eight circuits, while requiring only 19% additional runtime.
With semiconductor industry's aggressive march towards 45nm CMOS technology and introduction of new materials and device structures in sight for 32nm, and 22nm nodes, it is crucial for the IC design and CAD commun...
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ISBN:
(纸本)9781595933898
With semiconductor industry's aggressive march towards 45nm CMOS technology and introduction of new materials and device structures in sight for 32nm, and 22nm nodes, it is crucial for the IC design and CAD community to understand the challenges posed by these potential technology changes. This tutorial will focus on these challenges starting from front end of line (devices) to the back end of line (interconnects) and finally the impact on CAD. We will discuss the impact of various device technology options/improvements, such as high-kappa, metal gate, low temperature operation, increased mobility and reduced variability, on the overall chip performance in the context of power-constrained technology optimization. This will show that power constraints limit, bit do not eliminate, the performance improvements available from new technology. The integration issues related to low-K materials for interconnects in 45nm and beyond will be examined in the context of advanced IC design. Ultra low-K materials, evolution of etch and chemical mechanical polishing (CMP), and techniques to limit damage during processing and their impact on design performance will be discussed in detail. These advanced device and interconnect structures and materials including 3D technology have tremendous impact on the direction of the CAD industry. We will discuss the design methodology and CAD implications of these imminent technology changes.
We describe a SAT-based decision method for the underlying logic in many formal verification problems;i.e. the counter arithmetic logic with lambda expressions and uninterpreted functions (CLU). This logic is well sui...
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ISBN:
(纸本)1595933891
We describe a SAT-based decision method for the underlying logic in many formal verification problems;i.e. the counter arithmetic logic with lambda expressions and uninterpreted functions (CLU). This logic is well suited for equivalence checking of two versions of a hardware design or the input and output of a compiler and has been recently utilized in several model checkers. Our method follows the general Satisfiability Modulo Theories or SMT(T) framework and combines a DPLL-style SAT solver with two theory solvers;one specific to equality and the other to separation inequality atoms within CLU. By adopting a combined implication scheme, we coordinate the efforts among theory solvers, and by efficiently processing uninterpreted functions involved in conflicts, we considerably improve the effectiveness of SAT learning and backtracking routines. Finally, we empirically demonstrate the effectiveness of our SMT(CLU) procedure and compare its performance to recent solvers on a wide range of hardware verification benchmarks. Copyright 2006 acm.
In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a biclique-star replacement technique. In hierarchical timing analysis, each functional block is characterized int...
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ISBN:
(纸本)1595933891
In this paper, we propose a timing model reduction algorithm for hierarchical timing analysis based on a biclique-star replacement technique. In hierarchical timing analysis, each functional block is characterized into an abstract timing model. The complexity of analysis is linear to the number of edges in the abstract timing model for timing propagation. We propose a biclique-star replacement technique to minimize the number of edges in the timing model. The experiments on industry test cases show that by allowing acceptable errors, the proposed algorithm can largely reduce the number of edges in the timing model. Copyright 2006 acm.
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate performance models that export architectural...
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ISBN:
(纸本)1595933891
An approach to robust system level mixed signal design is presented based on analog platforms. The bottom-up characterization phase of platform components provides accurate performance models that export architectural constraints to the system level. From the one side, performance models can be affected by residual errors and usually do not consider process variations and modeling uncertainties. Conversely, behavioral models cannot match accurate circuit level simulations, so that during the mapping (exploration) process circuit configurations difficult to be realized may be obtained. We propose a methodology that extends techniques from optimization and design centering to system level analog design exploiting general, implicit architectural constraints to control the robustness of the solution. The approach allows quantitative extension of robust techniques to hierarchical designs. Its effectiveness is illustrated with the design of a pipeline A/D converter and a UMTS receiver front-end. Copyright 2006 acm.
In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhance the system performance and also to red...
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ISBN:
(纸本)1595933891
In real-time data-dominated communication and multimedia processing applications, due to the manipulation of large sets of data, a multi-layer memory hierarchy is used to enhance the system performance and also to reduce the energy consumption. Savings of dynamic energy can be obtained by accessing frequently used data from smaller memories rather than from large background memories. The optimization of the hierarchical memory architecture implies the addition of layers of smaller memories to which heavily used data can be copied. This paper presents a formal model for data reuse analysis which identifies those parts of arrays more intensely accessed, taking also into account the relative lifetimes of the signals. Tested on a two-layer memory hierarchy, this model led to savings in the dynamic energy from 40% to over 70% relative to the energy used in the case of a flat memory design. Copyright 2006 acm.
The proceedings contain 145 papers. The topics discussed include: microarchitecture parameter selection to optimize system performance under process variation;thermal sensor allocation and placement for reconfigurable...
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ISBN:
(纸本)1595933891
The proceedings contain 145 papers. The topics discussed include: microarchitecture parameter selection to optimize system performance under process variation;thermal sensor allocation and placement for reconfigurable systems;thermal characterization and optimization in platform FPGAs;performance analysis of concurrent systems with early evaluation;design automation for analog: the next generation of tool challenges;automation in mixed-signal design: challenges and solutions in the wake of the nano era;trunk decomposition based global routing optimization;optimizing yield in global routing;wire density driven global routing for CMP variation and timing;an analytical model for negative bias temperature instability;physical aware frequency selection for dynamic thermal management in multi-core systems;and a new RLC buffer insertion algorithm.
In this paper, we describe a new via-configurable routing architecture which shows much better throughput and performance than the previous structures. We demonstrate how to construct a single-via-mask fabric to reduc...
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ISBN:
(纸本)078039254X
In this paper, we describe a new via-configurable routing architecture which shows much better throughput and performance than the previous structures. We demonstrate how to construct a single-via-mask fabric to reduce further the mask cost, and we analyze the penalties which it incurs. To solve the routability problem commonly existing in fabric-based designs, an efficient white-space allocation scheme is suggested, which provides a fast design convergence and early prediction of the circuit mappability to a given fabric.
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