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Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine 24

Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Gonul, Yilmaz Ege Taskin, Baris Department of Electrical and Computer Engineering Drexel University PhiladelphiaPA United States

ISBN: (纸本)9798400710773

This paper presents a coupled ring oscillator based Potts machine to solve NP-hard combinatorial optimization problems (COPs). Potts model is a generalization of the Ising model, capturing multivalued spins in contrast to the binary-valued spins allowed in the Ising model. Similar to recent literature on Ising machines, the proposed architecture of Potts machines implements the Potts model with interacting spins represented by coupled ring oscillators. Unlike Ising machines which are limited to two spin values, Potts machines model COPs that require a larger number of spin values. A major novelty of the proposed Potts machine is the utilization of the N-SHIL (Sub-Harmonic Injection Locking) mechanism, where multiple stable phases are obtained from a single (i.e. ring) oscillator. In evaluation, 3-coloring problems from the DIMACS SATBLIB benchmark and two randomly generated larger problems are mapped to the proposed architecture. The proposed architecture is demonstrated to solve problems of varying size with 89% to 92% accuracy averaged over multiple iterations. The simulation results show that there is no degradation in accuracy, no significant increase in solution time, and only a linear increase in power dissipation with increasing problem sizes up to 2000 nodes. © 2024 Copyright is held by the owner/author(s).

关键词： Ising model

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HLSPilot: LLM-based High-Level Synthesis 24

HLSPilot: LLM-based High-Level Synthesis

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Xiong, Chenwei Liu, Cheng Li, Huawei Li, Xiaowei SKLP Institute of Computing Technology Chinese Academy of Sciences Beijing China Dept. of Computer Science University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798400710773

Large language models (LLMs) have catalyzed an upsurge in automatic code generation, garnering significant attention for register transfer level (RTL) code generation. Despite the potential of RTL code generation with natural language, it remains error-prone and limited to relatively small modules because of the substantial semantic gap between natural language expressions and hardware design intent. In response to the limitations, we propose a methodology that reduces the semantic gaps by utilizing C/C++ for generating hardware designs via High-Level Synthesis (HLS) tools. Basically, we build a set of C-to-HLS optimization strategies catering to various code patterns, such as nested loops and local arrays. Then, we apply these strategies to sequential C/C++ code through in-context learning, which provides the LLMs with exemplary C/C++ to HLS prompts. With this approach, HLS designs can be generated effectively. Since LLMs still face problems in determining the optimized pragma parameters precisely, we have a design space exploration (DSE) tool integrated for pragma parameter tuning. Furthermore, we also employ profiling tools to pinpoint the performance bottlenecks within a program and selectively convert bottleneck components to HLS code for hardware acceleration. By combining the LLM-based profiling, C/C++ to HLS translation, and DSE, we have established HLSPilot—the first LLM-enabled high-level synthesis framework, which can fully automate the high-level application acceleration on hybrid CPU-FPGA architectures. According to our experiments on real-world application benchmarks, HLSPilot achieve comparable performance in general and can even outperform manually crafted counterparts, thereby underscoring the substantial promise of LLM-assisted hardware designs. © 2024 Copyright is held by the owner/author(s).

关键词： High level synthesis

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2023 42nd ieee/acm international conference on computer-aided Design, ICCAD 2023 - Proceedings

2023 42nd IEEE/ACM International Conference on Computer-Aide...

引用

42nd ieee/acm international conference on computer-aided Design, ICCAD 2023

ISBN: (纸本)9798350315592

The proceedings contain 200 papers. The topics discussed include: Meltrix: a RRAM-based polymorphic architecture enhanced by function synthesis;PDNSig: identifying multi-tenant cloud FPGAs with power distribution network-based signatures;HAPIC: a scalable, lightweight and reactive cache for persistent-memory-based index;floorplanning for embedded multi-die interconnect bridge packages;CircuitOps: an ML infrastructure enabling generative AI for VLSI circuit optimization;FLEX : introducing flexible execution on CGRA with spatio-temporal vector dataflow;bespoke approximation of multiplication-accumulation and activation targeting printed multilayer perceptrons;side channel-assisted inference attacks on machine learning-based ECG classification;path-based processing using in-memory systolic arrays for accelerating data-intensive applications;and clock aware low power placement.

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Layout-level Hardware Trojan Prevention in the Context of Physical Design 24

Layout-level Hardware Trojan Prevention in the Context of Ph...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Tong, Xingyu Chen, Guohao Wei, Min Cai, Zhijie Zou, Peng Lin, Zhifeng Chen, Jianli State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China School of Microelectronics Fudan University Shanghai China Shanghai LEDA Technology Co. Ltd. Shanghai China School of Mathematics and Statistics Fuzhou University Fuzhou China

ISBN: (纸本)9798400710773

A growing recognition of potential vulnerabilities to layout-level Hardware Trojan (HT) attacks has spurred significant research efforts aimed at enhancing the resilience of ICs against such threats. However, traditional hardware security has been predominantly concerned with defensive measures, often overlooking the original key metrics in physical design evaluation: power, performance, and area (PPA). This study introduces an automated methodology incorporating HT considerations into the practical physical design process. Utilizing a Bayesian optimization framework, it effectively navigates the operation of commercial physical implementation tools in the solution space of hyper-parameter settings. Innovative strategies inspired by mosaic techniques, such as cell shifting and buffer insertion, realize additional improvements in layout-level trojan prevention. Comparative evaluations have shown that our approach outperforms leading entries from the ISPD 2023 Contest in terms of PPA and HT prevention metrics, thereby providing significant insights into the synergy between these critical factors. © 2024 Copyright is held by the owner/author(s).

关键词： computer viruses

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ChatOPU: An FPGA-based Overlay Processor for Large Language Models with Unstructured Sparsity 24

ChatOPU: An FPGA-based Overlay Processor for Large Language ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Zhao, Tiandong Lu, Shaoqiang Wu, Chen He, Lei University of California Los Angeles United States Shanghai Jiao Tong University China Ningbo Institute of Digital Twin Eastern Institute of Technology China

ISBN: (纸本)9798400710773

Large language models (LLMs) have achieved notable success on many applications with increasingly tremendous parameters and computations. While hardware accelerators on Transformer-based models have been extensively studied, recent work mainly assumes structured model pruning and does not work well for unstructured sparsity that could lead to more parameter and computation reduction. The reason behind is that it is difficult to exploit data reuse from the unstructured sparsity, leaving hardware underutilized. This paper proposes ChatOPU, an FPGA-based overlay processor for LLMs, to support unstructured model pruning with better data reuse. First, we propose a new diagonal dataflow on a systolic array to obtain efficient data reuse for both sparse and dense matrix multiplication. Second, we develop efficient encoding and decoding for the sparse parameters to save off-chip memory traffic. Moreover, we boost the off-chip bandwidth utilization with pinned on-chip KV cache allocation and coalesced access throughout the LLM inference. Experimental results show that ChatOPU on Xilinx U200 FPGA outperforms GPU and other FPGA-based accelerators on token/s by 2.29× and 1.63× on LLMs with unstructured sparsity across different input and output sequence lengths. © 2024 Copyright is held by the owner/author(s).

关键词： Storage allocation (computer)

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MORPH: More Robust ASIC Placement for Hybrid Region Constraint Management 24

MORPH: More Robust ASIC Placement for Hybrid Region Constrai...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Mai, Jing Zhang, Zuodong Lin, Yibo Wang, Runsheng Huang, Ru School of Computer Science Peking University China School of Integrated Circuits Peking University China Institute of EDA Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

Modern ASIC placement tools encompass three categories of region constraints: default regions, fence regions, and guide regions. Region constraints pose significant challenges to existing placement algorithms, compromising the versatility and robustness required for diverse placement workloads. In this work, we propose MORPH, a more robust ASIC placer designed for hybrid region constraints. We integrate hybrid region constraints into a unified multi-electrostatic formulation that features a shared electrostatics model and a binary-lifting-based region pruning algorithm. We develop a more robust nonlinear placement framework that includes second-order information and a hybrid-region-aware legalization algorithm to address convergence issues. Experiments on the ISPD 2015 benchmark suite demonstrate 5.6-14.3% HPWL improvement and 10-24% overflow reduction compared to state-of-the-art region-aware placers. Further experiments on the ISPD 2015 benchmark suite and its variants show that the proposed techniques can achieve over 30% HPWL improvement and up to a twofold reduction in overflow with more stable convergence. © 2024 Copyright is held by the owner/author(s).

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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement 24

Physically Aware Synthesis Revisited: Guiding Technology Map...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption. © 2024 Copyright is held by the owner/author(s).

关键词： Logic design

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Sustainable High-Performance Instruction Selection for Superscalar Processors 24

Sustainable High-Performance Instruction Selection for Super...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Sheikhpour, Saeideh Metz, David Jellum, Erling Själander, Magnus Eeckhout, Lieven Ghent University Belgium Norway

ISBN: (纸本)9798400710773

Sustainability is a grand societal challenge, which requires our urgent attention given the significant and growing contribution of electronic devices to global warming. The environmental footprint of an electronic device comprises of two major contributors: (1) the embodied footprint due to raw material extraction, manufacturing, assembly, end-of-life-processing, and (2) the operational footprint due to device use during its lifetime. Sustainable hardware design hence requires a holistic approach that encompasses the entire lifetime of an electronic device. In this paper, we demonstrate how to leverage conventional performance-power-area (PPA) analysis towards sustainable hardware design by investigating the sustainability-performance tradeoff of a non-trivial hardware circuitry, namely the dynamic instruction selection logic in superscalar processors. We assess five previously proposed complexity-effective and power-efficient instruction selection approaches compared to conventional out-of-order (OoO) selection, namely Casino, Load Slice Core (LSC), Forward Slice Core (FSC), Delay-and-Bypass (DnB) and Freeway. We find that Casino, FSC and OoO are Pareto-optimal, optimally balancing the environmental footprint against performance;in contrast, LSC, DnB and Freeway are suboptimal. In addition, based on these insights, we further improve FSC’s environmental footprint and propose FSC++ as a compelling sustainable design point: hardware synthesis to a 7 nm technology node and cycle-accurate FPGA simulation of complete SPEC CPU2017 benchmarks show that FSC++ reduces the environmental footprint by around 40% while degrading performance by only 1.7% compared to an OoO baseline. © 2024 Copyright is held by the owner/author(s).

关键词： computer hardware

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MEIC: Re-thinking RTL Debug Automation using LLMs 24

MEIC: Re-thinking RTL Debug Automation using LLMs

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Xu, Ke Sun, Jialin Hu, Yuchen Fang, Xinwei Shan, Weiwei Wang, Xi Jiang, Zhe National Center of Technology Innovation for EDA School of Integrated Circuits Southeast University China Department of Computer Science University of York United Kingdom

ISBN: (纸本)9798400710773

The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts. However, in the semiconductor industry, utilising LLMs to debug Register Transfer Level (RTL) code is still insufficient, largely due to the underrepresentation of RTL-specific data in training sets. This work introduces a novel framework, Make Each Iteration Count (MEIC), which contrasts with traditional one-shot LLM-based debugging methods that heavily rely on prompt engineering, model tuning, and model training. MEIC utilises LLMs in an iterative process to overcome the limitation of LLMs in RTL code debugging, which is suitable for identifying and correcting both syntax and function errors, while effectively managing the uncertainties inherent in LLM operations. To evaluate our framework, we provide an open-source dataset comprising 178 common RTL programming errors. The experimental results demonstrate that the proposed debugging framework achieves fix rate of 93% for syntax errors and 78% for function errors, with up to 48x speedup in debugging processes when compared with experienced engineers. The Repo. of dataset and code: https://***/SEU-ACAL/reproduce-MEIC-ICCAD. © 2024 Copyright is held by the owner/author(s).

关键词： Program debugging

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A Built-In Integrated Rowhammer, Rowpress, and Leakage Detection Sensor for DRAM 24

A Built-In Integrated Rowhammer, Rowpress, and Leakage Detec...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Rohbani, Nezam Pirayadi, Rouzbeh Soleimani, Mohammad Arman Kestelman, Adrian Cristal Unsal, Osman Sarbazi-Azad, Hamid Spain Department of Computer Engineering Sharif University of Technology Iran Barcelona Supercomputing Center Spain Department of Computer Engineering Sharif University of Technology Iran

ISBN: (纸本)9798400710773

The increasing density of DRAM chips has led to heightened susceptibility of memory cells to bit-flips. Rowhammer and Rowpress attacks on DRAMs have obtained significant attention due to their effectiveness in compromising system security and data integrity. A substantial portion of the previously proposed techniques for detecting rowhammer attacks focus on counting the number of row activations. However, these methods suffer from several limitations, including high overheads, lack of consideration for environmental conditions during DRAM operation, and limited tunability to detect rowpress attacks. To address these challenges, this work introduces a novel low-overhead built-in DRAM sensor designed specifically for detecting and locating rowhammer and rowpress attacks. The core idea behind the sensor is to utilize an additional non-operational DRAM sensor cell for each row. This auxiliary cell experiences the same potential rowhammer attacks as the other cells within that row. The sensor operates by controlling an extra precharged match-line based on the charge stored in the sensor cells. This sensor not only detects rowhammer attacks but also other environmental conditions that may impact DRAM cells retention time, such as temperature elevation or changes in operating voltage. Simulation results demonstrate that the proposed sensor detects all of the rowhammer attacks in the presence of process variation with a variance of up to 7.5% in circuit parameters. Furthermore, the area overhead introduced by the sensor remains about 1%, making it a promising solution for enhancing DRAM security with the minimum memory structure change. © 2024 Copyright is held by the owner/author(s).

关键词： Leak detection

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