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Sustainable High-Performance Instruction Selection for Superscalar Processors 24

Sustainable High-Performance Instruction Selection for Super...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Sheikhpour, Saeideh Metz, David Jellum, Erling Själander, Magnus Eeckhout, Lieven Ghent University Belgium Norway

ISBN: (纸本)9798400710773

Sustainability is a grand societal challenge, which requires our urgent attention given the significant and growing contribution of electronic devices to global warming. The environmental footprint of an electronic device comprises of two major contributors: (1) the embodied footprint due to raw material extraction, manufacturing, assembly, end-of-life-processing, and (2) the operational footprint due to device use during its lifetime. Sustainable hardware design hence requires a holistic approach that encompasses the entire lifetime of an electronic device. In this paper, we demonstrate how to leverage conventional performance-power-area (PPA) analysis towards sustainable hardware design by investigating the sustainability-performance tradeoff of a non-trivial hardware circuitry, namely the dynamic instruction selection logic in superscalar processors. We assess five previously proposed complexity-effective and power-efficient instruction selection approaches compared to conventional out-of-order (OoO) selection, namely Casino, Load Slice Core (LSC), Forward Slice Core (FSC), Delay-and-Bypass (DnB) and Freeway. We find that Casino, FSC and OoO are Pareto-optimal, optimally balancing the environmental footprint against performance;in contrast, LSC, DnB and Freeway are suboptimal. In addition, based on these insights, we further improve FSC’s environmental footprint and propose FSC++ as a compelling sustainable design point: hardware synthesis to a 7 nm technology node and cycle-accurate FPGA simulation of complete SPEC CPU2017 benchmarks show that FSC++ reduces the environmental footprint by around 40% while degrading performance by only 1.7% compared to an OoO baseline. © 2024 Copyright is held by the owner/author(s).

关键词： computer hardware

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MEIC: Re-thinking RTL Debug Automation using LLMs 24

MEIC: Re-thinking RTL Debug Automation using LLMs

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Xu, Ke Sun, Jialin Hu, Yuchen Fang, Xinwei Shan, Weiwei Wang, Xi Jiang, Zhe National Center of Technology Innovation for EDA School of Integrated Circuits Southeast University China Department of Computer Science University of York United Kingdom

ISBN: (纸本)9798400710773

The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts. However, in the semiconductor industry, utilising LLMs to debug Register Transfer Level (RTL) code is still insufficient, largely due to the underrepresentation of RTL-specific data in training sets. This work introduces a novel framework, Make Each Iteration Count (MEIC), which contrasts with traditional one-shot LLM-based debugging methods that heavily rely on prompt engineering, model tuning, and model training. MEIC utilises LLMs in an iterative process to overcome the limitation of LLMs in RTL code debugging, which is suitable for identifying and correcting both syntax and function errors, while effectively managing the uncertainties inherent in LLM operations. To evaluate our framework, we provide an open-source dataset comprising 178 common RTL programming errors. The experimental results demonstrate that the proposed debugging framework achieves fix rate of 93% for syntax errors and 78% for function errors, with up to 48x speedup in debugging processes when compared with experienced engineers. The Repo. of dataset and code: https://***/SEU-ACAL/reproduce-MEIC-ICCAD. © 2024 Copyright is held by the owner/author(s).

关键词： Program debugging

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A Built-In Integrated Rowhammer, Rowpress, and Leakage Detection Sensor for DRAM 24

A Built-In Integrated Rowhammer, Rowpress, and Leakage Detec...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Rohbani, Nezam Pirayadi, Rouzbeh Soleimani, Mohammad Arman Kestelman, Adrian Cristal Unsal, Osman Sarbazi-Azad, Hamid Spain Department of Computer Engineering Sharif University of Technology Iran Barcelona Supercomputing Center Spain Department of Computer Engineering Sharif University of Technology Iran

ISBN: (纸本)9798400710773

The increasing density of DRAM chips has led to heightened susceptibility of memory cells to bit-flips. Rowhammer and Rowpress attacks on DRAMs have obtained significant attention due to their effectiveness in compromising system security and data integrity. A substantial portion of the previously proposed techniques for detecting rowhammer attacks focus on counting the number of row activations. However, these methods suffer from several limitations, including high overheads, lack of consideration for environmental conditions during DRAM operation, and limited tunability to detect rowpress attacks. To address these challenges, this work introduces a novel low-overhead built-in DRAM sensor designed specifically for detecting and locating rowhammer and rowpress attacks. The core idea behind the sensor is to utilize an additional non-operational DRAM sensor cell for each row. This auxiliary cell experiences the same potential rowhammer attacks as the other cells within that row. The sensor operates by controlling an extra precharged match-line based on the charge stored in the sensor cells. This sensor not only detects rowhammer attacks but also other environmental conditions that may impact DRAM cells retention time, such as temperature elevation or changes in operating voltage. Simulation results demonstrate that the proposed sensor detects all of the rowhammer attacks in the presence of process variation with a variance of up to 7.5% in circuit parameters. Furthermore, the area overhead introduced by the sensor remains about 1%, making it a promising solution for enhancing DRAM security with the minimum memory structure change. © 2024 Copyright is held by the owner/author(s).

关键词： Leak detection

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Accurate, Yet Scalable: A SPICE-based Design and Optimization Framework for eNVM-based Analog In-memory Computing 24

Accurate, Yet Scalable: A SPICE-based Design and Optimizatio...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Mojahidul Ahsan, S.M. Shahriar, Muhammad Sakib Chowdhury, Mrittika Hossain, Tanvir Hasan, Md Sakib Hoque, Tamzidul Department of Electrical Engineering and Computer Science University of Kansas LawrenceKS United States Department of Electrical and Computer Engineering University of Mississippi OxfordMS United States

ISBN: (纸本)9798400710773

This paper introduces a scalable SPICE-based tool infrastructure designed to optimize analog compute-in-memory (ACIM) architectures utilizing emerging non-volatile resistive memory (eNVM) technologies. The inherent efficiency of analog eNVM crossbar arrays in performing matrix-vector multiplications significantly enhances the power, performance, and area efficiency of edge AI devices and other applications. Our framework addresses the challenges of accurately simulating ACIM architectures, which are highly susceptible to variations in process, voltage, temperature, and analog noise. The framework uses SPICE for accurate analog and mixed-signal circuit simulation. It automates the generation of SPICE-level ACIM designs for deep neural networks. Additionally, it speeds up the simulation runtime by up to 35× for large DNN models while maintaining the same SPICE-level accuracy. Moreover, it ensures simulation convergence for large netlists, facilitating SPICE simulation of large-scale eNVM crossbars that were previously impractical. We demonstrated that our framework is capable of simulating inference using netlists for MLPs with over 800,000 parameters trained on the MNIST dataset within acceptable runtime, where contemporary SPICE simulators do not even converge. We validated the simulation results in terms of inference accuracy, which shows less than a 3.8% accuracy drop compared to software-based inference results. Lastly, we demonstrated the integration of our framework with an architectural simulator, facilitating comprehensive system-level simulation. © 2024 Copyright is held by the owner/author(s).

关键词： Deep neural networks

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Co-Designing NVM-based Systems for Machine Learning and In-memory Search Applications 24

Co-Designing NVM-based Systems for Machine Learning and In-m...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Henkel, Jörg Siddhu, Lokesh Nassar, Hassan Bauer, Lars Chen, Jian-Jia Hakert, Christian Seidl, Tristan Chen, Kuan Hsun Hu, Xiaobo Sharon Li, Mengyuan Yang, Chia-Lin Wei, Ming-Liang Karlsruhe Institute of Technology Germany TU Dortmund Germany University of Twente Netherlands University of Notre Dame IN United States National Taiwan University Taiwan

ISBN: (纸本)9798400710773

With the rapid development of the Internet of Things, machine learning applications on edge devices with limited resources face challenges due to large data scales and irregular memory access patterns. Non-volatile memory (NVM) technologies provide promising solutions by offering larger capacity, low leakage power, and data persistence. In this paper, we discuss the potential of NVM technology in enhancing machine learning applications by improving energy efficiency and reducing latency through in-memory computation and different NVM write modes. The insights from this analysis provide valuable guidance to device researchers and system architects working to develop high-performance systems for machine learning and accelerators in large-scale search applications using NVMs. © 2024 Copyright is held by the owner/author(s).

关键词： computer aided instruction

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ConSmax: Hardware-Friendly Alternative Softmax with Learnable Parameters 24

ConSmax: Hardware-Friendly Alternative Softmax with Learnabl...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Liu, Shiwei Tao, Guanchen Zou, Yifei Chow, Derek Fan, Zichen Lei, Kauna Pan, Bangfei Sylvester, Dennis Kielian, Gregory Saligane, Mehdi Google Research United States Department of Electrical Engineering and Computer Sciences University of Michigan United States

ISBN: (纸本)9798400710773

The self-attention mechanism distinguishes transformer-based large language models (LLMs) apart from convolutional and recurrent neural networks. Despite the performance improvement, achieving real-time LLM inference on silicon remains challenging due to the extensive use of Softmax in self-attention. In addition to the non-linearity, the low arithmetic intensity significantly limits processing parallelism, especially when working with longer contexts. To address this challenge, we propose Constant Softmax (ConSmax), a software-hardware co-design that serves as an efficient alternative to Softmax. ConSmax utilizes differentiable normalization parameters to eliminate the need for maximum searching and denominator summation in Softmax. This approach enables extensive parallelization while still executing the essential functions of Softmax. Moreover, a scalable ConSmax hardware design with a bitwidth-split look-up table (LUT) can achieve lossless non-linear operations and support mixed-precision computing. Experimental results show that ConSmax achieves a minuscule power consumption of 0.2mW and an area of 0.0008mm2 at 1250MHz working frequency in 16nm FinFET technology. For open-source contribution, we further implement our design with the OpenROAD toolchain under SkyWater’s 130nm CMOS technology. The corresponding power is 2.69mW and the area is 0.007mm2. ConSmax achieves 3.35× power savings and 2.75× area savings in 16nm technology, and 3.15× power savings and 4.14× area savings with the open-source EDA toolchain. In the meantime, it also maintains comparable accuracy on the GPT-2 model and the WikiText103 dataset. The project is available at https://***/ReaLLMASIC/ConSmax. © 2024 Copyright is held by the owner/author(s).

关键词： Table lookup

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The Power of Graph Signal Processing for Chip Placement Acceleration 24

The Power of Graph Signal Processing for Chip Placement Acce...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798400710773

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear programming

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FlexHE: a Flexible Kernel Generation Framework for Homomorphic Encryption-Based Private Inference 24

FlexHE: a Flexible Kernel Generation Framework for Homomorph...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Yu, Jiangrui Zeng, Wenxuan Xu, Tianshi Chen, Renze Liang, Yun Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China School of Software and Microelectronics Peking University Beijing China School of Computer Science Peking University Beijing China

ISBN: (纸本)9798400710773

Secure two-party computation (2PC) based on homomorphic encryption (HE) achieves formal data privacy protection and gets increasing adoption for private deep neural network (DNN) inference. As modern HE schemes usually operate on polynomials, existing works rely on manually-designed HE kernels for representative DNN operations. However, this is not only unscalable considering the diverse operator types, shapes, polynomial orders, etc, but also misses important optimization opportunities. In this paper, we introduce FlexHE, a flexible kernel generation framework to enable automatic generation and optimization of HE kernels for 2PC-based private inference. Given a high-level description of DNN operations, FlexHE can systematically define the HE kernel design space considering various optimization dimensions, including loop tiling, reordering, etc. We also analyze the communication and computation impact of different optimization dimensions for design space reduction. To search for the best kernel design, a two-level optimization problem is formulated and iteratively solved with an integer linear programming (ILP) formulation. With extensive experimental results, we not only demonstrate a better coverage of DNN operations including depth-wise Conv3D and dilated Conv3D, but also achieve more than 100×, 7.9×, and 4.2× latency reduction compared to prior-art HElayers, Cheetah, and Falcon, respectively. © 2024 Copyright is held by the owner/author(s).

关键词： Linear programming

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ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models 24

ADO-LLM: Analog Design Bayesian Optimization with In-Context...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Yin, Yuxuan Wang, Yu Xu, Boxun Li, Peng Department of Electronic and Computer Engineering University of California Santa BarbaraCA United States

ISBN: (纸本)9798400710773

Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine-learning-based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black-box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high-dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM’s ability to infuse domain knowledge to rapidly generate viable design points to remedy BO’s inefficiency in finding high-value design areas specifically under the limited design space coverage of the BO’s probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high-quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO’s exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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MCUBERT: Memory-Efficient BERT Inference on Commodity Microcontrollers 24

MCUBERT: Memory-Efficient BERT Inference on Commodity Microc...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Yang, Zebin Chen, Renze Wu, Taiqiang Wong, Ngai Liang, Yun Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China School of Computer Science Peking University Beijing China The University of Hong Kong Hong Kong Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (纸本)9798400710773

In this paper, we propose MCUBERT to enable language models like BERT on tiny microcontroller units (MCUs) through network and scheduling co-optimization. We observe the embedding table contributes to the major storage bottleneck for tiny BERT models. Hence, at the network level, we propose an MCU-aware two-stage neural architecture search algorithm based on clustered low-rank approximation for embedding compression. To reduce the inference memory requirements, we further propose a novel fine-grained MCU-friendly scheduling strategy. Through careful computation tiling and re-ordering as well as kernel design, we drastically increase the input sequence lengths supported on MCUs without any latency or accuracy penalty. MCUBERT reduces the parameter size of BERT-tiny and BERT-mini by 5.7× and 3.0× and the execution memory by 3.5× and 4.3×, respectively. MCUBERT also achieves 1.5× latency reduction. For the first time, MCUBERT enables lightweight BERT models on commodity MCUs and processing more than 512 tokens with less than 256KB of memory. © 2024 Copyright is held by the owner/author(s).

关键词： Microcontrollers

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