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Post-placement rewiring and rebuffering by exhaustive search for functional symmetries

Post-placement rewiring and rebuffering by exhaustive search...

引用

ieee/acm international conference on computer aided Design

作者： Chang, KH Markov, IL Bertacco, V Univ Michigan Dept EECS Ann Arbor MI 48109 USA

ISBN: (纸本)078039254X

Separate optimizations of logic and layout have been thoroughly studied in the past and are well documented for common benchmarks. However, to be competitive, modern circuit optimizations must use physical and logic information simultaneously. In this work, we propose new algorithms for rewiring and rebuffering - a post-placement optimization that reconnects pins of a given netlist without changing the logic function and gate locations. These techniques are compatible with separate layout and logic optimizations, and appear independent of them. In particular, when the new optimization is applied before or after detailed placement, it approximately doubles the improvement in wirelength. Our contributions are based on exhaustive search for functional symmetries in sub-circuits consisting of several gates. Our graph-based symmetry finding is more comprehensive than previously known algorithms - it detects permutational and phase-shift symmetries on multiple input and output wires, as well as hybrid symmetries, creating more opportunities for rewiring and rebuffering.

关键词： computer aided design

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Clustering for processing rate optimization

Clustering for processing rate optimization

引用

ieee/acm international conference on computer aided Design

作者： Lin, C Wang, J Zhou, H Northwestern Univ Evanston IL 60208 USA

ISBN: (纸本)078039254X

Clustering (or partitioning) is a crucial step between logic synthesis and physical design in the layout of a large scale design. A design verified at the logic synthesis level may have timing closure problems at post-layout stages due to the emergence of multiple-clock-period interconnects. Consequently, a trade-off between clock frequency and throughput may be needed to meet the design requirements. In this paper, we find that the processing rate, defined as the product of frequency and throughput, of a sequential system is upper bounded by the reciprocal of its maximum cycle ratio, which is only dependent on the clustering. We formulate the problem of processing rate optimization as seeking an optimal clustering with the minimal maximum-cycle-ratio in a general graph, and present an iterative algorithm to solve it. Since our algorithm avoids binary search and is essentially incremental, it has the potential of being combined with other optimization techniques. Experimental results validate the efficiency of our algorithm.

关键词： computer aided logic design

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Parametric yield maximization using gate sizing based on efficient statistical power and delay gradient computation

Parametric yield maximization using gate sizing based on eff...

引用

ieee/acm international conference on computer aided Design

作者： Chopra, K Shah, S Srivastava, A Blaauw, D Sylvester, D Univ Michigan EECS Dept Ann Arbor MI 48109 USA

ISBN: (纸本)078039254X

With the increased significance of leakage power and performance variability, the yield of a design is becoming constrained both by power and performance limits, thereby significantly complicating circuit optimization. In this paper, we propose a new optimization method for yield optimization under simultaneous leakage power and performance limits. The optimization approach uses a novel leakage power and performance analysis that is statistical in nature and considers the correlation between leakage power and performance to enable accurate computation of circuit yield under power and delay limits. We then propose a new heuristic approach to incrementally compute the gradient of yield with respect to gate sizes in the circuit with high efficiency and accuracy. We then show how this gradient information can be effectively used by a non-linear optimizer to perform yield optimization. We consider both inter-die and intra-die variations with correlated and random components. The proposed approach is implemented and tested and we demonstrate up to 40% yield improvement compared to a deterministically optimized circuit.

关键词： computer aided design

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Design of DNA origami

Design of DNA origami

引用

ieee/acm international conference on computer aided Design

作者： Rothemund, PWK CALTECH Pasadena CA 91125 USA

ISBN: (纸本)078039254X

The generation of arbitrary patterns and shapes at very small scales is at the heart of our effort to miniaturize circuits and is fundamental to the development of nanotechnology. Here I review a recently developed method for folding long single strands of DNA into arbitrary two-dimensional shapes using a raster fill technique 'scaffolded DNA origami'. Shapes up to 100 nanometers in diameter can be approximated with a resolution of 6 nanometers and decorated with patterns of roughly 200 binary pixels at the same resolution. Experimentally verified by the creation of a dozen shapes an patterns, the method is easy, high yield, and lends itself well to automated design and manufacture. So far, CAD tools for scaffolded DNA origami are simple, require hand-design of the folding path, and are restricted to two dimensional designs. If the method gains wide acceptance, better CAD tools will be required.

关键词： DNA biomolecular electronics integrated circuit design integrated circuit manufacture nanopatterning 100 nm 6 nm CAD tools DNA origami automated design automated manufacture folding path raster fill technique computer-aided Design biomolecular electronics integrated circuit manufacture integrated circuit design Nanopatterning DNA origami

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Statistical timing analysis driven post-silicon-tunable clock-tree synthesis

Statistical timing analysis driven post-silicon-tunable cloc...

引用

ieee/acm international conference on computer aided Design

作者： Tsai, JL Zhang, LZ Chen, CCP Univ Wisconsin Dept Elect & Comp Engn Madison WI 53706 USA

ISBN: (纸本)078039254X

Process variations cause significant timing uncertainty and yield degradation in deep sub-micron technologies. A solution to counter timing uncertainty is post-silicon clock tuning. Existing design approaches for post-silicon-tunable (PST) clock-tree synthesis usually insert a PST clock buffer for each flip-flop or put PST clock buffers across an entire level of a clock-tree. This can cause significant over-design and long tuning time. In this paper, we propose to insert PST clock buffers at both internal and leaf nodes of a clock-tree and use a bottom-up algorithm to reduce the number of candidate PST clock buffer locations. We then provide two statistical-timing-driven optimization algorithms to reduce the hardware cost of a PST clock-tree. Experimental results on ISCAS89 benchmark circuits show that our algorithms achieve up to a 90% area or a 90% number of tunable clock buffer reductions compared to existing design methods.

关键词： computer aided design

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Fast thermal simulation for architecture level dynamic thermal management

Fast thermal simulation for architecture level dynamic therm...

引用

ieee/acm international conference on computer aided Design

作者： Liu, P Qi, ZY Li, H Jin, LL Wu, W Tan, SXD Yang, J Univ Calif Riverside Dept Elect Engn Riverside CA 92521 USA

ISBN: (纸本)078039254X

As power density increases exponentially, runtime regulation of operating temperature by dynamic thermal managements becomes necessary. This paper proposes a novel approach to the thermal analysis at chip architecture level for efficient dynamic thermal management. Our new approach is based on the observation that the power consumption of architecture level modules in microprocessors running typical workloads presents strong nature of periodicity. Such a feature can be exploited by fast spectrum analysis in frequency domain for computing steady state response. To obtain the transient temperature changes due to initial condition and constant power inputs, numerically stable moment matching approach is carried out. The total transient responses is the addition of the two simulation results. The resulting fast thermal analysis algorithm leads to at least 10x-100x speedup over traditional integration-based transient analysis with small accuracy loss.

关键词： computer aided design

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Architecture and details of a high quality, large-scale analytical placer

Architecture and details of a high quality, large-scale anal...

引用

ieee/acm international conference on computer aided Design

作者： Kahng, AB Reda, S Wang, QK Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

ISBN: (纸本)078039254X

Modem design requirements have brought additional complexities to netlists and layouts. Millions of components, whitespace resources, and fixed/movable blocks are just a few to mention in the list of complexities. With these complexities in mind, placers are faced with the burden of finding an arranggement of placeable objects under strict wirelength, timing, and power constraints. In this paper we describe the architecture and novel details of our high quality, large-scale analytical placer. The performance of our placer has been recently recognized in the recent ISPD-2005 placement contest, and in this paper we disclose many of the technical details that we believe are key factors to its performance. We describe (i) a new clustering architecture, (ii) a dynamically adaptive analytical solver, and (iii) better legalization schemes and novel detailed placement methods. We also provide extensive experimental results on a number of benchmark sets. On average, our results are better than the best published results by 3%, 14%, and 6% for the IBM ISPD'04, ICCAD'04, and ISPD'05 benchmark sets respectively. One of the goals of this paper is to also provide enough details to enable possible future replication of our methods.

关键词： computer aided design

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Complementary use of runtime validation and model checking

Complementary use of runtime validation and model checking

引用

ieee/acm international conference on computer aided Design

作者： Bayazit, AA Malik, S Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)078039254X

The increasing gap between design complexity and compute power for verification necessitates radically new solutions to meet the verification challenges for future generations of hardware designs. Increasingly it will not be possible to completely validate hardware prior to fabrication. We will need to reconcile ourselves to the fact that hardware, like software, will be shipped with bugs. However, this can be acceptable with appropriate mechanisms for runtime validation that detect bugs and recover from them when needed. This paper takes a significant step in examining runtime validation as part of the verification methodology. It examines the strengths and weaknesses of runtime validation and how it may be used to complement model checking in a hybrid methodology. We consider the use of on-chip hardware for detecting bugs using hardware assertions. These assertions may be used for validating abstractions and assumptions for use in offline model checking. Hardware based assertions monitor properties at runtime and do not suffer from the state explosion problem. Offline model checking is used to validate globally distributed properties where runtime error detection has limitations in monitoring and responding to signals separated by many clock cycles. In this case the hardware based runtime validated abstractions and assumptions help in reducing the state space for model checking. Our ideas are demonstrated on a highly concurrent, yet simple to understand token sharing protocol, as well as a fairly complex cache coherence system.

关键词： computer aided design

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Architecture and compilation for data bandwidth improvement in configurable embedded processors

Architecture and compilation for data bandwidth improvement ...

引用

ieee/acm international conference on computer aided Design

作者： Cong, J Han, GL Zhang, GF Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

ISBN: (纸本)078039254X

Many commercially available embedded processors are capable of extending their base instruction set for a specific domain of applications. While steady progress has been made in the tools and methodologies of automatic instruction set extension for configurable processors, recent study has shown that the limited data bandwidth available in the core processor (e.g., the number of simultaneous accesses to the register file) becomes a serious performance bottleneck. In this paper we propose a new low-cost architectural extension and associated compilation techniques to address the data bandwidth problem. Specifically, we embed a single control bit in the instruction op-codes to selectively copy the execution results to a set of hash-mapped shadow registers in the write-back stage. This can efficiently reduce the communication overhead due to data transfers between the core processor and the custom logic. We also present a novel simultaneous global shadow register binding with a hash function generation algorithm to take full advantage of the extension. The application of our approach leads to a nearly-optimal performance speedup (within 2% of the ideal speedup).

关键词： embedded systems integrated circuit design logic CAD microprocessor chips architectural extension techniques associated compilation techniques automatic instruction set configurable embedded processors core processor custom logic data bandwidth data tran computer aided logic design Microprocessor chips integrated circuit design Embedded systems PROCESSOR Collected papers register file configurability Bandwidth Building construction ARCHITECTURE instruction sets embedding

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IMF: Interconnect-driven multilevel floorplanning for large-scale building-module designs

IMF: Interconnect-driven multilevel floorplanning for large-...

引用

ieee/acm international conference on computer aided Design

作者： Chen, TC Chang, YW Lin, SC Natl Taiwan Univ Grad Inst Elect Engn Taipei 106 Taiwan

ISBN: (纸本)078039254X

We present in this paper a new interconnect-driven multilevel floorplanning, called IMF, to handle large-scale building-module designs. Unlike the traditional multilevel framework that adopts the "V-cycle" framework: bottom-up coarsening followed by top-down uncoarsening, in contrast, IMF works in the "Lambda-cycle" manner: top-down uncoarsening (partitioning) followed by bottom-up coarsening (merging). The top-down partitioning stage iteratively partitions the floorplan region based on min-cut bipartitioning with exact net-weight modeling to reduce the number of global interconnections and thus the total wirelength. Then, the bottom-up merging stage iteratively applies fixed-outline floorplanning using simulated annealing for all regions and merges two neighboring regions recursively. We also propose an accelerative fixed-outline floorplanning (AFT) to speed up wirelength minimization under the outline constraint. Experimental results show that IMF consistently obtains the best floorplanning results with the smallest wirelength for large-scale building-module designs, compared with all publicly available floorplanners. In particular, IMF scales very well as the circuit size increases. The Lambda-cycle multilevel framework outperforms the V-cycle one in the optimization of global circuit effects, such as interconnection and crosstalk optimization, since the Lambda-cycle framework considers the global configuration first and then processes down to local ones level by level and thus the global effects can be handled at earlier stages. The Lambda-cycle multilevel framework is general and thus can be readily applied to other problems.

关键词： computer aided design

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