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Compiler-directed voltage scaling on communication links for reducing power consumption

Compiler-directed voltage scaling on communication links for...

引用

ieee/acm international conference on computer aided Design

作者： Li, F Chen, G Kandemir, M Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA

ISBN: (纸本)078039254X

Reducing power consumption of communication networks is an important optimization goal in many application domains, ranging from large-scale simulation codes to embedded multi-media applications. Most of the prior efforts on network power optimization are hardware-based schemes. These schemes are predictive by definition as they control communication link status based on the observations made in the past. Since prediction may not be very accurate most of the time, these approaches can result in overheads in terms of both performance and power. This paper proposes a compiler-driven approach to communication link voltage management. In this approach, an optimizing compiler analyzes the application code and extracts the data communication pattern among parallel processors. This information along with network topology is used for identifying the link access patterns. These patterns and the inherent data dependence information of the underlying code help the compiler decide the optimum voltages/frequencies to be used for communication links at a given time frame. Our focus in this work is on loop-intensive codes which frequently appear in data intensive video and image processing. We exploit the regularity in data accesses of these codes to abstract out their inter-processor communication patterns, which in turn enable us select the most appropriate voltage/frequency level to employ for each communication link at any time.

关键词： computer networks data communication telecommunication links application code communication link voltage management compiler-directed voltage scaling data access data communication pattern data extraction data intensive video processing image processing Telecommunication links Access to Information information retrieval data communication computer network extracting data Image processing Power consumption compilers Codes Optimising compilers reduced power

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Computational geometry based placement migration

Computational geometry based placement migration

引用

ICCAD-2005: ieee/acm international conference on computer-aided Design, 2005

作者： Luo, Tao Ren, Haoxing Alpert, Charles J. Pant, David Z. Department of ECE University of Texas at Austin Austin TX 78712 IBM Corporation 11400 Burnet Road Austin TX 78758

ISBN: (纸本)078039254X

Placement migration is a critical step to address a variety of post-placement design closure issues, such as timing, routing congestion, signal integrity, and heat distribution. To fix a design problem, one would like to perturb the design as little as possible while preserving the integrity of the original placement. This work presents a novel computational geometry based placement migration method, and a new stability metric to more accurately measure the "similar-ity" between two placements. It has two stages, a bin-based spreading at coarse scale and a Delaunay triangulation based spreading at finer grain. It has clear advantage over conventional legalization algorithms such that the neighborhood characteristics of the original placement are preserved. Thus, the placement migration is much more stable, which is important to maintain. Applying this technique to placement legalization demonstrates significant improvements in wire length and stability compared to other popular legalization algorithms. ©2005 ieee.

关键词： computer aided design

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ICCAD-2005 international conference on computer aided Design

ICCAD-2005 International Conference on Computer Aided Design

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ICCAD-2005: ieee/acm international conference on computer-aided Design, 2005

ISBN: (纸本)078039254X

The proceedings contain 145 papers. The topics discussed include: storage assignment during high-level synthesis for configurable architectures;performance-driven read-after-write dependencies softening in high-level synthesis;an exact algorithm for the maximal sharing of partial terms in multiple constant multiplications;post-placement rewiring and rebuffering by exhaustive search for functional symmetries;wirelength optimization by optimal block orientation;parametric test development for RF circuits targeting physical fault locations and using specification-based fault definitions;test planning for the effective utilization of port-scalable testers for heterogeneous core-based SOCs;a cocktail approach on random access scan toward low power and high efficiency test;a statistical study of the effectiveness of BIST jitter measurement techniques;the circuit design of the synergistic processor element of a CELL processor;and a layout dependent full-chip copper electroplating topography model.

关键词： computer aided design

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Fast algorithms for IR drop analysis in large power grid

Fast algorithms for IR drop analysis in large power grid

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ICCAD-2005: ieee/acm international conference on computer-aided Design, 2005

作者： Zhong, Yu Wong, Martin D.F. Dept. of Electrical and Computer Engineering Univ. of Illinois at Urbana-Champaign Urbana IL 61801

ISBN: (纸本)078039254X

Due to the extremely large size of power grids, IR drop analysis has become a computationally challenging problem both in terms of runtime and memory usage. Although IR drop analysis can be naturally formulated as the problem of solving a linear system, the system is too large to be solved by existing linear solvers. In this paper, we present two iterative algorithms based on node-by-node traversals and row-by-row traversals of the power grid, respectively. Our algorithms are extremely fast and guarantee convergence to the exact solutions. In fact, they can be considered as efficient implementations of the classical Successive Over Relaxation iterative method for solving linear systems. Our methods take full advantage of the special structure of the power grid. Experimental results show that our algorithms out-perform the Random-Walk-based algorithm which is the best known method today. For a 16-million node problem, our row-based algorithm took 26.47 minutes while the Random-Walk-based algorithm took 19.6 hours. Our row-based algorithm produced an exact solution while the Random Walk produced a solution with maximum error of 5.7 mV. ©2005 ieee.

关键词： Electric power distribution

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ICCAD-2005 international conference on computer aided Design: Foreword

IEEE/ACM International Conference on Computer-Aided Design, ...

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ieee/acm international conference on computer-aided Design, digest of Technical Papers, ICCAD 2005年 2005卷

作者： Sarrafzadeh, Majid Hassoun, Soha

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ISBN: (纸本)078039254X

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ieee/acm international conference on computer-aided Design, digest of Technical Papers, ICCAD: Foreword

IEEE/ACM International Conference on Computer-Aided Design, ...

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ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Onodera, Hidetoshi Sarrafzadeh, Majid

No abstract available

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ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

ICCAD-2004 - IEEE/ACM International Conference on Computer-A...

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ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

The proceedings contain 135 papers from the ICCAD - 2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers. The topics discussed include: statistical design and optimization of SRAM cell for yield enhancement;DAG-aware circuit compression for formal verification;dynamic transition relation simplification for bounded property checking;fast simulation of VLSI interconnects;a soft error rate analysis (SERA) methodology;the care and feeding of your statistical static timer;a robust cell-level crosstalk delay change analysis;delay noise pessimism reduction by logic correlations;debugging sequential circuits using Boolean satisfiability;and towards formal verification of analog designs.

关键词： computer aided design

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m-Trie: An efficient approach to on-chip logic minimization 04

m-Trie: An efficient approach to on-chip logic minimization

引用

international conference on computer aided Design (ICCAD 2004)

作者： Ahmad, S Mahapatra, R Texas A&M Univ Dept Comp Sci College Stn TX 77843 USA

ISBN: (纸本)0780387023

Boolean logic minimization is being increasingly applied to new applications which demands very fast and frequent minimization services. These applications typically offer very limited computing and memory resources rendering the traditional logic minimizers ineffective. We present a new approximate logic minimization algorithm based on ternary trie. We compare its performance with Espresso-II and ROCM logic minimizers for routing table compaction and demonstrate that it is 100 to 1000 times faster and can run with a data memory as little as 16KB. It is also found that proposed approach can support up to 25000 incremental updates per seconds positioning itself as an ideal on-chip logic minimization algorithm.

关键词： Application software Routing Logic devices Minimization methods Compaction Logic circuits Circuit synthesis Network synthesis computer science Boolean functions

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Voltage-drop-constrained optimization of power distribution network based on reliable maximum current estimates 04

Voltage-drop-constrained optimization of power distribution ...

引用

international conference on computer aided Design (ICCAD 2004)

作者： Evmorfopoulos, NE Karampatzakis, DP Stamoulis, GI Univ Thessaly Dept Comp & Commun Engn Volos 38221 Greece

ISBN: (纸本)0780387023

The problem of optimum design of tree-shaped power distribution networks with respect to the voltage drop effect is addressed in this paper. An approach for the width adjustment of the power lines supplying the circuit's major functional blocks is formulated, so that the network occupies the minimum possible area under specific voltage drop constraints at all blocks. The optimization approach is based on precise maximum current estimates derived by statistical means from recent advances in the field of extreme value theory. Experimental tests include the design of power grid for a choice of different topologies and voltage drop tolerances in a typical benchmark circuit.

关键词： Voltage Power systems Design methodology computer network reliability Telecommunication network reliability Circuit testing Wires Circuit noise Logic circuits Power distribution lines

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Automated oscillator macromodelling techniques for capturing amplitude variations and injection locking 04

Automated oscillator macromodelling techniques for capturing...

引用

international conference on computer aided Design (ICCAD 2004)

作者： Lai, XL Roychowdhury, J Univ Minnesota Dept Elect & Comp Engn Minneapolis MN 55455 USA

ISBN: (纸本)0780387023

We present a method for extracting comprehensive amplitude and phase macromodels of oscillators from their circuit descriptions. The macromodels are based on combining a scalar, nonlinear phase equation with a small linear time-varying system to capture slowly-dying amplitude variations. The comprehensive macromodels are able to correctly predict oscillator response in the presence of interference at far lower computational cost than that of full SPICE-level simulation. We also present an efficient numerical method for capturing injection locking in oscillators, thereby improving on the classic technique of Adler [1] in terms of accuracy and applicability to any kind of oscillator. We demonstrate the proposed techniques on LC and ring oscillators, comparing results from the macromodels against full SPICE-like simulation. Numerical experiments demonstrate speedups of orders of magnitude, while retaining excellent accuracy.

关键词： Injection-locked oscillators Circuit simulation Computational modeling Frequency Ring oscillators Nonlinear equations Clocks computer simulation SPICE Interference

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