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A unified theory of timing budget management 04

A unified theory of timing budget management

引用

international conference on computer aided Design (ICCAD 2004)

作者： Ghiasi, S Bozorgzadeh, E Choudhuri, S Sarrafzadeh, M Univ Calif Los Angeles Dept Comp Sci Los Angeles CA 90095 USA

ISBN: (纸本)0780387023

This paper presents a theoretical framework that optimally solves many open problems in time budgeting. Our approach unifies a large class of existing time-management paradigms. Examples include time budgeting for maximizing total weighted delay relaxation, minimizing the maximum relaxation and min-skew time budget distribution. We show that many of the time management problems can be transformed into a min-cost flow instance that can be optimally and efficiently solved through well-known combinatorial techniques. Experiments include mapping of several designs, which are implemented using parameterized CoreGen IP cores, on Xilinx FPGA devices. Different time budgeting policies have been applied during the mapping stage. Our time management techniques always improved the area requirement of the implemented testbenches compared to a widely-used path-based method. We also compared the maximum budgeting and fairness in delay budget assignments. Our experimental results show that an average improvement of 19% in area can be achieved when fairness and maximum budgeting policies are combined, compared to pure maximum budgeting.

关键词： Timing Financial management Libraries computer science Field programmable gate arrays Delay Power system management Design optimization Power dissipation Runtime

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High-level synthesis using computation-unit integrated memories 04

High-level synthesis using computation-unit integrated memor...

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international conference on computer aided Design (ICCAD 2004)

作者： Huang, C Ravi, S Raghunathan, A Jha, NK Princeton Univ Dept Elect Engn Princeton NJ 08544 USA

ISBN: (纸本)0780387023

High-level synthesis (HLS) of memory-intensive applications has featured several innovations in terms of enhancements made to the basic memory organization and data layout. However, increasing performance and energy demands faced by application-specific integrated circuits (ASICs) are forcing designers to alter the fundamental architectural template of the HLS output, namely, a controller-datapath associated with a memory subsystem (monolithic, banked, etc.). In this paper, we propose an architectural template for the HLS output that consists of a controller-datapath circuit associated with a memory subsystem into which computation units have been integrated. The enhanced memory subsystem is called computation-unit integrated memory (CIM). A CIM offers higher memory bandwidth (relative to what is offered through the system bus) to computation units present locally within it and reduces the overall communication between the memory subsystem and the controller-datapath, thus providing a template highly suitable for deriving efficient implementations of memory-intensive applications. This work addresses the challenge of providing an automatic synthesis framework for a CIM-based architecture. Our framework can analyze the various trade-offs involved in selecting suitable operations in a behavior for execution using a CIM and generate a high-performance, low-overhead implementation. Experiments with several behaviors indicate that an average performance improvement of 1.88X (a maximum of 2.63X) is possible with very low area overheads. The energy-delay product improves by an average of 2.1 X (maximum of 3.4 X).

关键词： High level synthesis computer integrated manufacturing Application specific integrated circuits Communication system control Technological innovation Bandwidth System buses Automatic control Control systems Control system synthesis

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Verifying properties of hardware and software by predicate abstraction and model checking

Verifying properties of hardware and software by predicate a...

引用

ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Bryant, Randal E. Rajamani, Sriram K. Carnegie Mellon University Pittsburgh PA United States Microsoft Research Redmond WA United States

The use of two verification tools UCLID, that verifies the hardware systems modeled at a word level and SLAM, a tool to prove properties of programs written in C programming languages was discussed. It was found that both support predicate abstraction in which the state of the system was characterized by a set of Boolean predicates. The properties range from simple rules about ordering of function calls to data-dependent properties that require the tool to keep track of value-flow and aliasing. The Boolean program model was a viable approach for checking the properties that were strongly dependent on control flow of sequential programs.

关键词： computer aided software engineering

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Checking consistency of C and Verilog using predicate abstraction and induction

Checking consistency of C and Verilog using predicate abstra...

引用

ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Kroening, Daniel Clarke, Edmund Computer Systems Institute ETH Zürich Zürich Switzerland Computer Science Dept. Carnegie Mellon University Pittsburgh PA United States

It is common practice to write C models of circuits due to the greater simulation efficiency. Once the C program satisfies the requirements, the circuit is designed in a hardware description language (HDL) such as Verilog. It is therefore highly desirable to automatically perform a correspondence check between the C model and a circuit given in HDL. We present an algorithm that checks consistency between an ANSI-Cprogram and a circuit given in Verilog using Predicate Abstraction. The algorithm exploits the fact that the C program and the circuit share many basic predicates. In contrast to existing tools that perform predicate abstraction, our approach is S AT-based and allows all ANSI-C and Verilog operators in the predicates. We report experimental results on an out-of-order RISC processor. We compare the performance of the new technique to Bounded Model Checking (BMC). ©2004 ieee.

关键词： C (programming language)

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Analyzing software influences on substrate noise: An ADC perspective 04

Analyzing software influences on substrate noise: An ADC per...

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ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Kang, Byungtae Vijaykrishnan, N. Irwin, Mary Jane Samsung Korea Republic of Dept. of CSE Penn State University Univ. Park PA United States

ISBN: (纸本)0780387023

Substrate noise affects the performance of mixed signal integrated circuits. Power supply (di/dt) noise is the dominant source of substrate noise. There have been various attempts at the circuit and software levels to estimate this noise. Software-level noise estimation is especially important, as designing noise tolerant circuits for all circumstances may be prohibitively expensive. In this paper, we propose a new software approach for estimating di/dt noise and incorporate it into a power simulator in order to investigate the influence of software on substrate noise. As a case study, we investigate how an analog-to-digital converter (ADC) can be designed to adapt its resolution in the presence of substrate noise generated by a embedded processor core. The proposed strategies prevent unexpected ADC performance degradations. © 2004 ieee.

关键词： computer software

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Debugging sequential circuits using Boolean satisfiability

Debugging sequential circuits using Boolean satisfiability

引用

ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Ali, Moayad Fahim Veneris, Andreas Safarpour, Sean Drechsler, Rolf Smith, Alexander Abadir, Magdy University of Toronto Department of Electrical Engineering Toronto Ont. M5S 3G4 University of Toronto Department of Computer Science Toronto Ont. M5S 3G4 University of Bremen Department of Computer Science 28359 Bremen Freescale Semiconductor Inc. Austin TX 78729

Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean Satisfiability. This formulation takes advantage of modern Boolean Satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean Satisfiability provides an effective platform for sequential logic debugging. © 2004 ieee.

关键词： Sequential circuits

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Code partitioning for synthesis of embedded applications with phantom

Code partitioning for synthesis of embedded applications wit...

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ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Nácul, André C. Givargis, Tony Department of Computer Science University of California Irvine

In a large class of embedded systems, dynamic multitasking using traditional OS techniques is infeasible because of memory and processing overheads or lack of operating systems availability for the target embedded processor. Serializing compilers have been proposed as an alternative solution, enabling a designer to develop multitasking applications without the need of OS support. A serializing compiler is a source-to-source translator that takes a POSIX compliant multitasking C program as input and generates an equivalent, embedded processor independent, single-threaded ANSI C program, to be compiled using the embedded processor-specific tool chain. Such serializing compilers work by partitioning each task into blocks of code and synthesizing a scheduler that dynamically switches among these blocks. The quality of the compiled code in terms of multitasking overhead and task latency is highly dependent on the partitioning algorithm. In this work, we give our solution to the partitioning problem in the context of serializing compilers. We show that it is possible to provide the designer with a set of Pareto-Optimal solutions that trade off multitasking overhead for task latency. © 2004 ieee.

关键词： Embedded systems

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Temporal floorplanning using the T-tree formulation

Temporal floorplanning using the T-tree formulation

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ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Yuh, Ping-Hung Yang, Chia-Lin Chang, Yao-Wen Department of Computer Science National Taiwan University Taipei Taiwan Dept. of Electrical Engineering Grad. Inst. of Electron. Engineering National Taiwan University Taipei Taiwan

Improving logic capacity by time-sharing, dynamically reconfigurable FPGAs are employed to handle designs of high complexity and functionality. In this paper, we model each task as a 3D-box and deal with the temporal floorplanning/placement problem for dynamically reconfigurable FPGA architectures. We present a tree-based data structure, called T-trees, to represent the spatial and temporal relations among tasks. Each node in a T-tree has at most three children which represent the dimensional relationship among tasks. For the T-tree, we develop an efficient packing method and derive the condition to ensure the satisfaction of precedence constraints which model the temporal ordering among tasks induced by the execution of dynamically reconfigurable FPGAs. Experimental results show that our tree-based formulation can achieve significantly better solution quality with less execution time than the most recent state-of-the-art work. ©2004 ieee.

关键词： Field programmable gate arrays

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HiSIM: Hierarchical interconnect-centric circuit simulator

HiSIM: Hierarchical interconnect-centric circuit simulator

引用

ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Chen, Tsung-Hao Tsai, Jeng-Liang Chen, Charlie C.-R. Karnik, Tanay Synopsys Inc. Electrical and Computer Engineering University of Wisconsin Madison Grad. Inst. of Electron. Engineering National Taiwan University Intel Corp.

To ensure the power and signal integrity of modern VLSI circuits, it is crucial to analyze huge amount of nonlinear devices together with enormous interconnect and even substrate parasitics to achieve the required accuracy. Neither traditional circuit simulation engines such as SPICE nor switch-level timing analysis algorithms are equipped to handle such a tremendous challenge in both efficiency and accuracy. In this paper, we establish a solid framework that simultaneously takes advantage of a novel hierarchical non-linear circuit simulation algorithm and an advanced large-scale linear circuit simulation method using a new predictor-corrector algorithm. Under solid convergence and stability guarantees, our simulator, HiSIM, a hierarchical interconnect-centric circuit simulator, is capable of handling the post-layout RLKC power and signal integrity analysis task efficiently and accurately. Experimental results demonstrate over 180X speed up over the conventional flat simulation method with SPICE-level accuracy. ©2004 ieee.

关键词： Electric network analysis

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Optimizing mode transition sequences in idle intervals for component-level and system-level energy minimization

Optimizing mode transition sequences in idle intervals for c...

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ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Liu, Jinfeng Chou, Pai H. Center for Embedded Computer Systems University of California Irvine CA 92697-2625 United States

New embedded systems offer rich power management features in the form of multiple operational and non-operational power modes. While they offer mechanisms for better energy efficiency, they also complicate power management decisions in the presence of real-time constraints. Traditional dynamic power management techniques based on localized break-even-time analysis with simple on/off power controls often yield suboptimal if not incorrect results globally. To address these problems, this paper presents two core algorithms for reducing idle energy consumption at the component level and system level. The first algorithm discovers the optimal sequence for mode transition over multiple power modes under timing constraints. It assists the second algorithm that performs a sophisticated global search strategy to aggressively explore system-wide energy savings by correctly interpreting the constraints across all subsystems. Experimental results show that in an embedded radio system where idle energy cost matches or exceeds the active energy consumption, our technique can further reduce the idle energy by 50-70%, which translates into 30-50% of overall system energy compared to existing techniques. ©2004 ieee.

关键词： Embedded systems

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