检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

879 篇 会议
11 篇 期刊文献

馆藏范围

890 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

630 篇 工学
- 549 篇 计算机科学与技术...
- 434 篇 软件工程
- 261 篇 电气工程
- 261 篇 电子科学与技术（可...
- 78 篇 机械工程
- 48 篇 控制科学与工程
- 35 篇 信息与通信工程
- 31 篇 动力工程及工程热...
- 15 篇 材料科学与工程（可...
- 14 篇 冶金工程
- 14 篇 生物工程
- 11 篇 生物医学工程（可授...
- 10 篇 仪器科学与技术
- 10 篇 化学工程与技术
- 8 篇 建筑学
- 6 篇 光学工程
- 5 篇 力学（可授工学、理...
- 5 篇 土木工程
283 篇 理学
- 240 篇 数学
- 47 篇 物理学
- 38 篇 统计学（可授理学、...
- 16 篇 系统科学
- 14 篇 化学
- 14 篇 生物学
46 篇 管理学
- 42 篇 管理科学与工程(可...
- 17 篇 工商管理
- 4 篇 图书情报与档案管...
11 篇 法学
- 9 篇 社会学
6 篇 经济学
- 6 篇 应用经济学
3 篇 农学
2 篇 教育学
2 篇 艺术学
1 篇 医学

主题

126 篇 computer aided d...
82 篇 computer aided l...
78 篇 computer science
52 篇 computer archite...
49 篇 timing
41 篇 delay
39 篇 permission
37 篇 routing
35 篇 very large scale...
31 篇 circuit simulati...
31 篇 integrated circu...
30 篇 circuit testing
30 篇 clocks
30 篇 hardware
27 篇 computational mo...
27 篇 circuits
26 篇 circuit faults
25 篇 circuit synthesi...
25 篇 energy consumpti...
25 篇 algorithm design...

机构

16 篇 computer science...
8 篇 computer systems...
8 篇 univ calif los a...
7 篇 department of el...
6 篇 department of el...
5 篇 department of el...
5 篇 school of comput...
5 篇 beijing advanced...
5 篇 stanford univ ca...
5 篇 department of co...
5 篇 department of co...
5 篇 school of integr...
5 篇 computer science...
5 篇 department of co...
4 篇 ucla united stat...
4 篇 univ of californ...
4 篇 electrical and c...
4 篇 department of el...
4 篇 department of el...
4 篇 synopsys inc. mo...

作者

16 篇 cong jason
14 篇 m. potkonjak
9 篇 wong d.f.
9 篇 m. sarrafzadeh
8 篇 j. cong
8 篇 d.f. wong
7 篇 koh cheng-kok
7 篇 c.l. liu
7 篇 cheng chung-kuan
7 篇 lim sung kyu
6 篇 kahng andrew b.
6 篇 anon
6 篇 wong martin d.f.
6 篇 sarrafzadeh maji...
6 篇 d. kirovski
5 篇 li peng
5 篇 gang qu
5 篇 gajski daniel d.
5 篇 liu c.l.
5 篇 potkonjak miodra...

语言

845 篇 英文
41 篇 其他
4 篇 中文

检索条件"任意字段=IEEE/ACM International Conference on Computer Aide Digest"

共 890 条记录，以下是331-340 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Unification of partitioning, placement and floorplanning

Unification of partitioning, placement and floorplanning

引用

ICCAD-2004 - ieee/acm international conference on computer-aided Design, digest of Technical Papers

作者： Adya, Saurabh N. Chaturvedi, Shubhyant Roy, Jarrod A. Papa, David A. Markov, Igor L. Synplicity Inc. 600 W. California Ave. Sunnyvale CA 95054 Advanced Micro Devices Austin TX 78741 University of Michigan EECS Department Ann Arbor MI 48109-2122

Large macro blocks, pre-designed datapaths, embedded memories and analog blocks are increasingly used in ASIC designs. However, robust algorithms for large-scale placement of such designs have only recently been considered in the literature, and improvements by over 10% per paper are still common. Large macros can be handled by traditional floorplanning, but are harder to account for in min-cut and analytical placement. On the other hand, traditional floorplanning techniques do not scale to large numbers of objects, especially in terms of solution quality. We propose to integrate min-cut placement with fixed-outline floorplanning to solve the more general placement problem, which includes cell placement, floorplanning, mixed-size placement and achieving routability. At every step of min-cut placement, either partitioning or wirelength-driven, fixed-outline floorplanning is invoked. If the latter fails, we undo an earlier partitioning decision, merge adjacent placement regions and re-floorplan the larger region to find a legal placement for the macros. Empirically, this framework improves the scalability and quality of results for traditional wirelength-driven floorplanning. It has been validated on recent designs with embedded memories and accounts for routability. Additionally, we propose that free-shape rectilinear floorplanning can be used with rough module-area estimates before synthesis. ©2004 ieee.

关键词： Storage allocation (computer)

来源：评论

学校读者我要写书评

暂无评论

Debugging sequential circuits using Boolean satisfiability 04

Debugging sequential circuits using Boolean satisfiability

引用

international conference on computer aided Design (ICCAD 2004)

作者： Ali, MF Veneris, A Safarpour, S Drechsler, R Smith, A Abadir, M Univ Toronto Dept Elect & Comp Engn Toronto ON M5S 3G4 Canada

ISBN: (纸本)0780387023

Logic debugging of today's complex sequential circuits is an important problem. In this paper, a logic debugging methodology for multiple errors in sequential circuits with no state equivalence is developed. The proposed approach reduces the problem of debugging to an instance of Boolean Satisfiability. This formulation takes advantage of modern Boolean Satisfiability solvers that handle large circuits in a computationally efficient manner. An extensive suite of experiments with large sequential circuits confirm the robustness and efficiency of the proposed approach. The results further suggest that Boolean Satisfiability provides an effective platform for sequential logic debugging.

关键词： Debugging Sequential circuits Very large scale integration Fault diagnosis Robustness Logic design computer science Boolean functions computer bugs Design automation

来源：评论

学校读者我要写书评

暂无评论

Formal verification coverage: computing the coverage gap between temporal specifications 04

Formal verification coverage: computing the coverage gap bet...

引用

international conference on computer aided Design (ICCAD 2004)

作者： Das, S Basu, P Banerjee, A Dasgupta, P Chakrabarti, PP Mohan, CR Fix, L Armoni, R Indian Inst Technol Dept Comp Sci & Engn Kharagpur W Bengal India

ISBN: (纸本)0780387023

Existing methods for formal verification coverage compare a given specification with a given implementation, and evaluate the coverage gap in terms of quantitative metrics. In this paper, we consider a new problem, namely to compare two formal temporal specifications and to find a set of additional temporal properties that close the coverage gap between the two specifications. In this paper we present: (1) the problem definition and motivation, (2) a methodology for computing the coverage gap between specifications, and (3) a methodology for representing the coverage gap as a collection of temporal properties that preserve the syntactic structure Of the target specification.

关键词： Formal verification Formal specifications Logic computer science Strategic planning

来源：评论

学校读者我要写书评

暂无评论

Improving soft-error tolerance of FPGA configuration bits 04

Improving soft-error tolerance of FPGA configuration bits

引用

international conference on computer aided Design (ICCAD 2004)

作者： Srinivasan, S Gayasen, A Vijaykrishnan, N Kandemir, M Xie, Y Irwin, MJ Penn State Univ Dept Comp Sci & Engn University Pk PA 16802 USA

ISBN: (纸本)0780387023

Soft errors that change configuration bits of an SRAM based FPGA modify the functionality of the design. The proliferation of FPGA devices in various critical applications makes it important to increase their immunity to soft errors. In this work, we propose the use of an asymmetric SRAM (ASRAM) structure that is optimized for soft error immunity and leakage when storing a preferred value. The key to our approach is the observation that the configuration bitstream is composed of 87% of zeros across different designs. Consequently, the use of ASRAM cell optimized for storing a zero (ASRAM-0) reduces the failure in time by 25% as compared to the original design. We also present an optimization that increases the number of zeros in the bitstream while preserving the functionality.

关键词： Field programmable gate arrays Random access memory Routing computer errors Capacitance Error analysis Table lookup Multiplexing computer science Design engineering

来源：评论

学校读者我要写书评

暂无评论

Incremental deductive & inductive reasoning for SAT-based Bounded Model Checking 04

Incremental deductive & inductive reasoning for SAT-based Bo...

引用

international conference on computer aided Design (ICCAD 2004)

作者： Zhang, L Prasad, MR Hsiao, MS Virginia Tech Dept Elect & Comp Engn Blacksburg VA 24061 USA

ISBN: (纸本)0780387023

Bounded Model Checking (BMC) based on Boolean Satisfiability (SAT) methods has recently gained popularity as a viable alternative to BDD-based techniques for verifying large designs. This work proposes a number of conceptually simple, but extremely effective, optimizations for enhancing the performance of SAT-based BMC flows. The keys ideas include (1) a novel idea to combine SAT-based inductive reasoning and BMC, (2) clever orchestration of variable ordering and learned information in an incremental framework for BMC, and (3) BMC-specific ordering strategies for the SAT solver. Our experiments, conducted on a wide range of industrial designs, show that the proposed optimizations consistently provide between 1-2 orders of magnitude speedup and can be extremely useful in enhancing the efficacy of typical SAT-BMC tools.

关键词： Data structures Boolean functions Design engineering Laboratories Design optimization Hardware Product design computer bugs Formal verification Explosions

来源：评论

学校读者我要写书评

暂无评论

An analytic placer for mixed-size placement and timing-driven placement 04

An analytic placer for mixed-size placement and timing-drive...

引用

international conference on computer aided Design (ICCAD 2004)

作者： Kahng, AB Wang, Q Univ Calif San Diego Dept Comp Sci & Engn La Jolla CA 92093 USA

ISBN: (纸本)0780387023

We extend the APlace wirelength-driven standard-cell analytic placement framework of [21] to address timing-driven and mixed-size ("boulders and dust") placement. Compared with timing-driven industry tools, evaluated by commercial detailed routing and STA, we achieve an average of 8.4% reduction in cycle time and 7.5% reduction in wirelength for a set of six industry testcases. For mixed-size placement, we achieve an average of 4% wirelength reduction on ISPD02 mixed-size placement benchmarks [18] compared to results of the leading-edge solver, Feng Shui (v2.4) [25]. We are currently evaluating our placer on industry testcases that combine the challenges of timing constraints, large instance sizes, and embedded blocks (both fixed and unfixed).

关键词： computer science Routing Benchmark testing Timing Very large scale integration Productivity Integrated circuit interconnections Smoothing methods

来源：评论

学校读者我要写书评

暂无评论

Efficient SAT-based unbounded symbolic model checking using circuit cofactoring 04

Efficient SAT-based unbounded symbolic model checking using ...

引用

international conference on computer aided Design (ICCAD 2004)

作者： Ganai, MK Gupta, A Ashar, P NEC Labs Amer Princeton NJ 08540 USA

ISBN: (纸本)0780387023

We describe an efficient approach for SAT-based quantifier elimination that significantly improves the performance of pre-image and fixed-point computation in SAT-based unbounded symbolic model checking (UMC). The proposed method captures a larger set of new states per SAT-based enumeration step during quantifier elimination, in comparison to previous approaches. The novelty of our approach is in the use of circuit-based cofactoring to capture a large set of states, and in the use of a functional hashing based simplified circuit graph to represent the captured states. We also propose a number of heuristics to further enlarge the state set represented per enumeration, thereby reducing the number of enumeration steps. We have implemented our techniques in a SAT-based UMC framework where we show the effectiveness of SAT-based existential quantification on public benchmarks, and on a number of large industry designs that were hard to model check using purely BDD-based techniques. We show several orders of improvement in time and space using our approach over previous CNF-based approaches. We also present controlled experiments to demonstrate the role of several heuristics proposed in the paper. Importantly, we were able to prove using our method the correctness of a safety property in an industry design that could not be proved using other known approaches.

关键词： Circuits Data structures Boolean functions Safety computer bugs State-space methods National electric code Laboratories Robustness Design methodology

来源：评论

学校读者我要写书评

暂无评论

ieee/acm international conference on computer-aided Design, digest of Technical Papers: Foreword

IEEE/ACM International Conference on Computer-Aided Design, ...

引用

ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Kuehlmann, Andreas Onodera, Hidetoshi

来源：评论

学校读者我要写书评

暂无评论

ILP models for the synthesis of asynchronous control circuits

ILP models for the synthesis of asynchronous control circuit...

引用

ieee/acm international conference on computer aided Design (ICCAD 2003)

作者： Carmona, J Cortadella, J Univ Politecn Cataluna Comp Architecture Dept Barcelona 08860 Spain

ISBN: (纸本)1581137621

A new technique for the logic synthesis of asynchronous circuits is presented. It is based on the structural theory of Petri nets and integer linear programming. The technique is capable of checking implementability conditions, such as, complete state coding, and deriving a gate netlist to implement the specified behavior. This technique can synthesize specifications with few thousands of transitions in the Petri net, providing a speed-up of several orders of magnitude with regard to other existing techniques.

关键词： computer aided design

来源：评论

学校读者我要写书评

暂无评论

Power-optimal simultaneous buffer insertion/sizing and wire sizing

Power-optimal simultaneous buffer insertion/sizing and wire ...

引用

ieee/acm international conference on computer aided Design (ICCAD 2003)

作者： Li, RM Zhou, D Liu, J Zeng, X Univ Texas Sch Engn & Comp Sci Richardson TX 75083 USA

ISBN: (纸本)1581137621

This paper studies the problems of minimizing power dissipation of an interconnect wire by simultaneously considering buffer insertion/sizing and wire sizing (BISWS). We consider two cases, namely minimizing power dissipation with optimal delay constraints, and minimizing power dissipation with a given delay penalty. We derive closed form optimal solutions for both cases. These closed form solutions can be used to efficiently estimate the power dissipation in the early stages of the VLSI designs. We observe that the power dissipation can be much different even with the same optimal delay.

关键词： computer aided design

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共89页 << < 30 31 32 33 34 35 36 37 38 39 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：