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Approaching the maximum energy saving on embedded systems with multiple voltages

Approaching the maximum energy saving on embedded systems wi...

引用

ieee/acm international conference on computer aided Design (ICCAD 2003)

作者： Hua, SX Qu, G Univ Maryland Elect & Comp Engn Dept College Pk MD 20742 USA

ISBN: (纸本)1581137621

Dynamic voltage scaling (DVS) is arguably the most effective energy reduction technique. The multiple-voltage DVS systems, which can operate only at pre-determined discrete voltages, are practical and have been well studied. However, one important unsolved problem is how many levels and at which values should voltages be implemented on a multiple-voltage DVS system to achieve the maximum energy saving. We refer this as the voltage set-up problem. In this paper, (1) we derive analytical solutions for dual-voltage system. (2) For the general case that does not have analytic solutions, we develop efficient numerical methods. (3) We demonstrate how to apply the proposed algorithms on system design. (4) Interestingly, the experimental results suggest that the multiple-voltage DVS system, when the voltages are set up properly, can reach DVS technique's full potential in energy saving. Specifically, on the design of an ad hoc application-specific system and the design of the MPEG video encoder, we find that the best single-voltage systems consume 150% and 20% more energy than the tight theoretical lower bounds, respectively. However, our approach gives dual-, 3-, and 4-voltage DVS system settings that are only 17.6%, 4.9%, and 2.6% for the ad hoc system, and 4.0%, 1.1%, and 0.2% for the MPEG video encoder, over the same lower bounds.

关键词： computer aided logic design

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On Application of Output Masking to Undetectable Faults in Synchronous Sequential Circuits with Design-for-Testability Logic

On Application of Output Masking to Undetectable Faults in S...

引用

ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Pomeranz, Irith Reddy, Sudhakar M. Sch. of Electrical and Computer Eng. Purdue University W. Lafayette IN 47907 United States Electrical Eng. Dept. University of Iowa Iowa City IA 52242 United States

Design-for-testability (DFT) for synchronous sequential circuits causes redundant faults in the original circuit to be detectable in the circuit with DFT logic. It has been argued that such faults should not be detected in order to avoid reducing the yield unnecessarily. One way to deal with such faults is to mask (or ignore) their fault effects when they appear on the circuit outputs, without masking the detection of faults that need to be detected. To investigate the extent to which this can be accomplished, we describe a procedure for masking the effects of redundant faults of the original circuit under a given test set generated for the circuit with DFT logic. The procedure attempts to maximize the number of redundant faults that are masked while minimizing (or holding to zero) the number of other masked faults.

关键词： Sequential circuits

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Large-Scale Circuit Placement: Gap and Promise

Large-Scale Circuit Placement: Gap and Promise

引用

ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Cong, Jason Kong, Tim Shinnerl, Joseph R. Xie, Min Yuan, Xin UCLA Computer Science Department United States Magma Design Automation

Placement is one of the most important steps in the RTL-to-GDSII synthesis process, as it directly defines the inter-connects, which have become the bottleneck in circuit and system performance in deep submicron technologies. The placement problem has been studied extensively in the past 30 years. However, recent studies show that existing placement solutions are surprisingly far from optimal. The first part of this tutorial summarizes results from recent optimality and scalability studies of existing placement tools. These studies show that the results of leading placement tools from both industry and academia may be up to 50% to 150% away from optimal in total wirelength. If such a gap can be closed, the corresponding performance improvement will be equivalent to several technology-generation advancements. The second part of the tutorial highlights the recent progress on large-scale circuit placement, including techniques for wire-length minimization, routability optimization, and performance optimization.

关键词： Integrated circuit layout

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Bus-Driven Floorplanning

Bus-Driven Floorplanning

引用

ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Xiang, Hua Tang, Xiaoping Wong, Martin D.F. CS Dept. UIUC Urbana IL 61801 Cadence Design Systems San Jose CA 95134 ECE Dept. UIUC Urbana IL 61801

In this paper, we present an integrated approach to floorplanning and bus planning, i.e., bus-driven floorplanning (BDF). We are given a set of circuit blocks and the bus specifications (i.e., the net list of blocks for the buses). A feasible BDF solution is a placement of all circuit blocks such that each bus can be realized as a rectangular strip (horizontal or vertical) going through all the blocks connected by the bus. The objective is to determine a feasible BDF solution that minimizes floorplan area and total bus area. Our approach is based upon the sequence-pair floorplan representation. After a careful analysis of the relationship between bus ordering and block ordering in the floorplan represented by a sequence pair, we derive feasibility conditions on sequence pairs that give feasible BDF solutions. Experimental results demonstrate the efficiency and effectiveness of our algorithm.

关键词： computer aided design

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A probabilistic approach to buffer insertion

A probabilistic approach to buffer insertion

引用

ieee/acm international conference on computer aided Design (ICCAD 2003)

作者： Khandelwal, V Davoodi, A Nanavati, A Srivastava, A Univ Maryland Dept Elect & Comp Engn College Pk MD 20742 USA

ISBN: (纸本)1581137621

This work presents a formal probabilistic approach for solving optimization problems in design automation. Prediction accuracy is very low especially at high levels of design flow. This can be attributed mainly to unawareness of low level layout information and variability in fabrication process. Hence a traditional deterministic design automation approach where each cost function is represented as a fixed value becomes obsolete. A new approach is gaining attention [13, 5, 2, 4, 10] in which the cost functions are represented as probability distributions and the optimization criteria is probabilistic too. This design optimization philosophy is demonstrated through the classic buffer insertion problem [11]. Formally, we capture wirelengths as probability distributions (as compared to the traditional approach which considers wirelength as fixed values) and present several strategies for optimizing the probabilistic criteria. During the course of this work many problems are proved to be NP-Complete. Comparisons are made with the Van-Ginneken 11 optimal under fixed wire-length" algorithm. Results show that the Van-Ginneken approach generated delay distributions at the root of the fanout wiring tree which had large probability (0.91 in the worst case and 0.55 on average) of violating the delay constraint. Our algorithms could achieve 100% probability of satisfying the delay constraint with similar buffer penalty. Although this work considers wirelength prediction inaccuracies, our probabilistic strategy could be extended trivially to consider fabrication variability in wire parasitics.

关键词： computer aided design

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Achieving Design Closure Through Delay Relaxation Parameter

Achieving Design Closure Through Delay Relaxation Parameter

引用

ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Srivastava, Ankur Memik, Seda Ogrenci Choi, Bo-Kyung Sarrafzadeh, Majid ECE Department University of Maryland College Park MD United States Computer Science Department University of California Los Angeles CA United States

Current design automation methodologies are becoming incapable of achieving design closure especially in the presence of deep submicron effects. This paper addresses the issue of design closure from a high level point of view. A new metric called delay relaxation parameter (DRP)for RTL (Register Transfer Level) designs is proposed. DRP essentially captures the degree of delay relaxation that the design can tolerate without violating the clock constraint. This metric when optimized results in quicker design flow. Algorithms to optimize DRP are formulated and their optimality are investigated. Experimental results are conducted using a state of the an design flow with Synopsys Design Compiler followed by Cadence Place and Route. Our approach of optimizing DRP resulted in lesser design iterations and faster design closure as compared to designs generated through Synopsys Behavioral Compiler and a representative academic design flow.

关键词： computer aided logic design

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Efficient Generation of Monitor Circuits for GSTE Assertion Graphs

Efficient Generation of Monitor Circuits for GSTE Assertion ...

引用

ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Hu, Alan J. Casas, Jeremy Yang, Jin Dept. of Computer Science University of British Columbia Canada Strategic CAD Lab. Intel Corporation United States

Generalized symbolic trajectory evaluation (GSTE) is a powerful, new method for formal verification that combines the industriallyproven scalability and capacity of classical symbolic trajectory evaluation with the expressive power of temporal-logic model checking. GSTE was originally developed at Intel and has been used successfully on Intel's next-generation microprocessors. However, the supporting algorithms and tools for GSTE are still relatively immature. GSTE specifications are given as assertion graphs, an extension of ∀-automata. This paper presents a linear-time, linear-size translation from GSTE assertion graphs into monitor circuits, which can be used with dynamic verification both as a quick "sanity check" of the specification before effort is invested in abstraction and formal verification, and also as means to reuse GSTE specifications with other validations methods. We present experimental results using real GSTE assertion graphs for real industrial circuits, showing that the circuit construction procedure is efficient in practice and that the monitor circuits impose minimal simulation overhead.

关键词： Formal logic

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Fault-Tolerant Techniques for Ambient Intelligent Distributed Systems

Fault-Tolerant Techniques for Ambient Intelligent Distribute...

引用

ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Marculescu, Diana Zamora, Nicholas H. Stanley-Marbell, Phillip Marculescu, Radu Department of Electrical Engineering Carnegie Mellon University Pittsburgh PA 15213-3890 United States

Ambient Intelligent Systems provide an unexplored hardware platform for executing distributed applications under strict energy constraints. These systems must respond quickly to changes in user behavior or environmental conditions and must provide high availability and fault-tolerance under given quality constraints. These systems will necessitate fault-tolerance to be built into applications. One way to provide such fault-tolerance is to employ the use of redundancy. Hundreds of computational devices will be available in deeply networked ambient intelligent systems, providing opportunities to exploit node redundancy to increase application lifetime or improve quality of results if it drops below a threshold. Pre-copying with remote execution is proposed as a novel, alternative technique of code migration to enhance system lifetime for ambient intelligent systems. Self-management of the system is considered in two different scenarios: applications that tolerate graceful quality degradation and applications with single-point failures. The proposed technique can be part of a design methodology for prolonging the lifetime of a wide range of applications under various types of faults, despite scarce energy resources.

关键词： Distributed computer systems

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Adjustable Width Linear Combinational Scan Vector Decompression

Adjustable Width Linear Combinational Scan Vector Decompress...

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ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Krishna, C.V. Touba, Nur A. Computer Engineering Research Center University of Texas Austin TX 78712-1084 United States

A new scheme for combinational linear expansion is proposed for decompression of scan vectors. It has the capability to adjust the width of the linear expansion each clock cycle. This eliminates the requirement that every scan bit-slice be in the output space of the linear decompressor. Depending on how specified the current bit-slice is, the decompressor may load all scan chains or may load only a subset of the scan chains. This provides the nice feature that any scan vector can be generated using the proposed scheme regardless of the number or distribution of the specified bits. Thus, the proposed scheme allows the use of any ATPG procedure without any constraints. Moreover, it allows greater compression to be achieved than fixed width expansion techniques since the ratio of the number of scan chains to the number of tester channels can be scaled much larger. A procedure for designing and optimizing the adjustable width decompression hardware and obtaining the compressed data is described. Experimental data indicates that the proposed scheme is simple yet very effective.

关键词： Data compression

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Adaptive error protection for energy efficiency

Adaptive error protection for energy efficiency

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ieee/acm international conference on computer aided Design ICCAD 2003: ieee/acm digest of Technical Papers

作者： Li, Lin Vijaykrishnan, N. Kandemir, Mahmut Irwin, Mary Jane Microsystems Design Lab Pennsylvania State University University Park PA 16802

With dramatic scaling in feature sizes, noise resilience is becoming one of the most important design parameters, similar to performance and energy efficiency. Noise resilience is particularly problematic in long on-chip buses of complex single chip systems such as on-chip multiprocessors. While one might opt to employ a very powerful error protection scheme, this may not be very energy efficient as noise behavior typically varies over time. In this paper, we propose an adaptive error protection scheme for energy efficiency, where the type of the coding scheme is modulated dynamically. The idea behind this strategy is to monitor the dynamic variations in noise behavior and use the least powerful (and hence the most energy efficient) error protection scheme required to maintain the error rates below a pre-set threshold. Our detailed experimental results obtained through simulation show that this adaptive strategy achieves the same level of error protection as the most powerful strategy experimented, without experiencing the latter's energy inefficiency. Based on our results, we recommend system designers to adopt adaptive protection schemes in environments where both energy and reliability are important.

关键词： computer aided logic design

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