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BPINN-EM: Fast Stochastic Analysis of Electromigration Damage using Bayesian Physics-Informed Neural Networks 24

BPINN-EM: Fast Stochastic Analysis of Electromigration Damag...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Lamichhane, Subed Kavousi, Mohamadamir Tan, Sheldon X.-D. Department of Electrical and Computer Engineering University of California RiversideCA92521 United States

ISBN: (纸本)9798400710773

Electromigration (EM) induced aging and degradation in interconnect wires is inherently a stochastic process, with lifetime typically measured in terms of mean time to failure at both wire and circuit levels. However, existing approaches still incur high computing costs, as computing both means and variances is generally expensive. In this work, we propose a novel fast variational analysis framework to tackle the challenges of stochastic estimation of EM stress evolution in multi-segment interconnect wires. We utilize Bayesian networks in conjunction with the recently introduced hierarchical (two-step) physics-informed neural networks (PINN). The resulting method, termed BPINN-EM, enables rapid variational stress analysis of metal wires by leveraging the robust uncertainty quantification capability of Bayesian networks with expedited training over small dataset. Moreover, we devise BPINN-EM to incorporate Bayesian networks only in the first stage of the hierarchical PINN, thereby circumventing the need for sampling across the entire PINN level during training and significantly reducing training costs. Our results on several general multi-segment interconnect structure demonstrate that the proposed BPINN-EM approach is much more efficient than conventional baselines and state-of-the-art algorithms. Compared to a Monte Carlo simulator implemented in COMSOL, BPINN-EM offers a 240× speedup. Moreover, compared to the recently proposed EMSpice simulated by the Monte Carlo method, the new method provides more than an 85× speedup with almost no loss of accuracy. © 2024 Copyright is held by the owner/author(s).

关键词： Monte Carlo methods

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FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity 24

FSMM: An Efficient Matrix Multiplication Accelerator Support...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Qiao, Yuxuan Yang, Fan Zhang, Yecheng Xiong, Xiankui Yao, Xiao Yao, Haidong State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China School of Microelectronics Fudan University Shanghai China State Key Laboratory of Mobile Network and Mobile Multimedia Technology ZTE Corporation Shenzhen China

ISBN: (纸本)9798400710773

Sparse matrix multiplication is a critical operation in deep learning. However, matrix sparsity leads to irregular data flow, which would degrade the efficiency of matrix multiplication. Traditional accelerators, equipped with additional hardware units to address this issue, often experience the issue of low hardware utilization. Furthermore, N : M structured sparsity and corresponding hardware architectures face challenges such as accuracy degradation, limited flexibility, and restricted applicability. In this paper, we propose a Flexible Sparse Matrix Multiplication Accelerator (FSMM), which can improve the efficiency of sparse matrix multiplication through both algorithmic-level and hardware-level optimizations. At the algorithmic level, we propose the matrix-matrix multiplication with block-level outer production and fine-grained matrix reordering algorithm. The algorithm balances the sparsity of each column of a matrix block, which improves matrix compression, balances the load, and speeds up computation. This algorithm reduces storage by 8.2% ~ 85.9%. At the hardware-level, we introduce a flexible architecture for matrix multiplication. It selects the most suitable data path to complete matrix multiplication based on the sparsity of the reordered matrix. FSMM achieves a speedup of 1.90× ~ 16.18× over Systolic Array and 1.70× ~ 2.87× over the existing TSTC approach. © 2024 Copyright is held by the owner/author(s).

关键词： Fast response computer systems

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Equivalence Checking for Flow-Based Computing using Iterative SAT Solving 24

Equivalence Checking for Flow-Based Computing using Iterativ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Thijssen, Sven Rashed, Muhammad Rashedul Haq Ahmed, Md Rubel Singireddy, Suraj Jha, Sumit Kumar Ewetz, Rickard Department of Electrical Engineering and Computer Science Florida Atlantic University Boca RatonFL United States Department of Computer Science and Engineering University of Texas at Arlington ArlingtonTX United States Department of Electrical and Computer Engineering University of Central Florida OrlandoFL United States Department of Electrical and Computer Engineering University of Texas at San Antonio San AntonioTX United States Knight Foundation School of Computing and Information Sciences Florida International University MiamiFL United States Department of Electrical and Computer Engineering University of Florida GainesvilleFL United States

ISBN: (纸本)9798400710773

Processing in-memory is projected to shatter the von Neumann bottleneck and enable acceleration of data-intensive applications. Flow-based computing is an efficient in-memory computing paradigm for accelerating the execution of Boolean logic. While recent synthesis algorithms can map complex functions into flow-based computing circuits, the functional correctness cannot be verified using state-of-the-art equivalence checking techniques. The challenge is that non-volatile memory devices are intrinsically bi-directional, which introduces cycles in the computational graph. These cycles break traditional equivalence checking methods that are based on SAT formulations. In this paper, we propose a framework for equivalence checking of flow-based computing circuits that is called FlowSAT. The framework captures each circuit using an undirected computational graph. The key idea of FlowSAT is to introduce helper variables, in the form of arrows, that dynamically convert the undirected graph into a directed graph. This facilitates equivalence checking to be performed using traditional SAT formulations. However, it is prohibitively expensive to ban all possible cycles using arrow variables. Therefore, we propose to eliminate cycles by iteratively adding constraints to the SAT formulation. Our experimental evaluation demonstrates that FlowSAT is up to an order of magnitude faster than state-of-the-art methods. The framework is capable of verifying all 20/20 benchmark circuits, while the previous state-of-the-art technique is only capable of verifying 12/20 circuits within a time limit of one hour. © 2024 Copyright is held by the owner/author(s).

关键词： Data flow graphs

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HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method 24

HeLEM-GR: Heterogeneous Global Routing with Linearized Expon...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Zhao, Chunyuan Guo, Zizheng Wang, Rui Wen, Zaiwen Liang, Yun Lin, Yibo School of Integrated Circuits Peking University China Institute of EDA Peking University China School of Mathematics Southwestern University of Finance and Economics China Beijing International Center for Mathematical Research Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

Global routing (GR) plays an important role in the VLSI design flow. It not only serves as guidance for the follow-up detailed routing but also provides early design feedback for floorplanning and placement. Global routing engines are desired to provide a high-quality solution within a short time. With the design complexity growing, it becomes increasingly challenging to resolve routing overflow within affordable runtime. For example, ISPD 2024 GPU/ML-enhanced global routing contest has released large-scale industrial cases, which contain up to 50 million cells and 60 million signal nets, causing huge challenges to existing routing algorithms. In this paper, we propose HeLEM-GR, based on the linearized exponential multiplier method and heterogeneous routing kernels to achieve high-quality and ultrafast routing solutions. Our linearized exponential multiplier method can quickly reduce routing overflow. The routing process is extremely fast with GPU-enhanced massive parallelization. Experimental results demonstrate that we can achieve 4.8%-5.8% better quality scores and 1.62×-2.07× speedup compared with the top-3 winners in the ISPD 2024 contest. © 2024 Copyright is held by the owner/author(s).

关键词： Digital arithmetic

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Invited Paper: Learned In-Sensor Visual Computing: From Compression to Eventification 42

Invited Paper: Learned In-Sensor Visual Computing: From Comp...

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42nd ieee/acm international conference on computer-aided Design, ICCAD 2023

作者： Feng, Yu Ma, Tianrui Boloor, Adith Zhu, Yuhao Zhang, Xuan University of Rochester Department of Computer Science United States Washington University Department of Electrical and Systems Engineering St. Louis United States

ISBN: (纸本)9798350315592

Visual computing is vital for numerous applications. In conventional visual computing systems, CMOS image sensors (CIS) act as pure imaging devices for capturing images, however, recent CIS designs increasingly integrate processing capabilities such as Deep Neural Networks (DNN), which give rise to a notion of in-sensor computing. In this paper, we propose a new concept, learned in-sensor visual computing, which exploits end-to-end optimization of in-sensor processing and downstream vision tasks to achieve better overall algorithm accuracy and adopts hardware/algorithm co-design to achieve ultra-low sensor energy consumption. Two examples of the learned in-sensor visual computing, Leca and EDGAzE, are demonstrated. © 2023 ieee.

关键词： Deep neural networks

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Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment 24

Co-Designing Binarized Transformer and Hardware Accelerator ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Ji, Yuhao Fang, Chao Ma, Shaobo Shao, Haikuo Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (纸本)9798400710773

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing model size, existing approaches suffer from algorithm-hardware mismatches with limited co-design exploration, leading to suboptimal performance on edge devices. Hence, we propose a co-design method for efficient end-to-end edge deployment of Transformers from three aspects: algorithm, hardware, and joint optimization. First, we propose BMT, a novel hardware-friendly binarized Transformer with optimized quantization methods and components, and we further enhance its model accuracy by leveraging the weighted ternary weight splitting training technique. Second, we develop a streaming processor mixed binarized Transformer accelerator, namely BAT, which is equipped with specialized units and scheduling pipelines for efficient inference of binarized Transformers. Finally, we co-optimize the algorithm and hardware through a design space exploration approach to achieve a global trade-off between accuracy, latency, and robustness for real-world deployments. Experimental results show our co-design achieves up to 2.14~49.37× throughput gains and 3.72~88.53× better energy efficiency over state-of-the-art Transformer accelerators, enabling efficient end-to-end edge deployment. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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EPipe: Pipeline Inference Framework with High-quality Offline Parallelism Planning for Heterogeneous Edge Devices 24

EPipe: Pipeline Inference Framework with High-quality Offlin...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Xiong, Yi Liu, Weihong Zhang, Rui Zu, Yulong Zhu, Zongwei Zhou, Xuehai School of Computer Science and Technology University of Science and Technology of China China Suzhou Institute for Advanced Research University of Science and Technology of China China School of Software Engineering University of Science and Technology of China China

ISBN: (纸本)9798400710773

Pipeline parallelism is essential for edge computing as it effectively consolidates the limited resources of edge devices, enabling the deployment of large Deep Neural Network (DNN) models and accelerating inference processes without compromising the performance of models. Accurate computation and communication latency estimation on heterogeneous edge devices is essential for searching for a superior parallelism plan. However, existing heterogeneous pipeline inference approaches either incur substantial resource wastage during online parallelism planning, as they utilize profiling strategies that occupy physical devices;or rely on cost models with inadequate representational capabilities, leading to inaccurate predictions, thereby harming the result of pipeline planning. This paper proposes EPipe, a novel pipeline inference framework that supports high-quality offline planning in heterogeneous edge environments. EPipe integrates two core components: the Task-Device Co-analyzer (TDC) and the Multi-pipeline Parallelism Planner (MPP). TDC utilizes an undirected connected graph to depict the compatibility of DNNs across device groups and precisely estimates inference and communication latencies through fine-grained modeling. Based on TDC, MPP utilizes a dynamic programming-based genetic algorithm to explore multi-pipeline solutions, extending beyond traditional single-pipeline methods. A comprehensive experimental evaluation on an edge testbed confirms the effectiveness of EPipe, demonstrating significant speedups in inference tasks for both task streams and single tasks. © 2024 Copyright is held by the owner/author(s).

关键词： Edge detection

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HLSPilot: LLM-based High-Level Synthesis 24

HLSPilot: LLM-based High-Level Synthesis

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Xiong, Chenwei Liu, Cheng Li, Huawei Li, Xiaowei SKLP Institute of Computing Technology Chinese Academy of Sciences Beijing China Dept. of Computer Science University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798400710773

Large language models (LLMs) have catalyzed an upsurge in automatic code generation, garnering significant attention for register transfer level (RTL) code generation. Despite the potential of RTL code generation with natural language, it remains error-prone and limited to relatively small modules because of the substantial semantic gap between natural language expressions and hardware design intent. In response to the limitations, we propose a methodology that reduces the semantic gaps by utilizing C/C++ for generating hardware designs via High-Level Synthesis (HLS) tools. Basically, we build a set of C-to-HLS optimization strategies catering to various code patterns, such as nested loops and local arrays. Then, we apply these strategies to sequential C/C++ code through in-context learning, which provides the LLMs with exemplary C/C++ to HLS prompts. With this approach, HLS designs can be generated effectively. Since LLMs still face problems in determining the optimized pragma parameters precisely, we have a design space exploration (DSE) tool integrated for pragma parameter tuning. Furthermore, we also employ profiling tools to pinpoint the performance bottlenecks within a program and selectively convert bottleneck components to HLS code for hardware acceleration. By combining the LLM-based profiling, C/C++ to HLS translation, and DSE, we have established HLSPilot—the first LLM-enabled high-level synthesis framework, which can fully automate the high-level application acceleration on hybrid CPU-FPGA architectures. According to our experiments on real-world application benchmarks, HLSPilot achieve comparable performance in general and can even outperform manually crafted counterparts, thereby underscoring the substantial promise of LLM-assisted hardware designs. © 2024 Copyright is held by the owner/author(s).

关键词： High level synthesis

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ShiftCAM: A Time-Domain Content Addressable Memory Utilizing Shifted Hamming Distance for Robust Genome Analysis 24

ShiftCAM: A Time-Domain Content Addressable Memory Utilizing...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： He, Peiyi Mao, Ruibin Shan, Keyi Tong, Yunwei Xu, Zhicheng Peng, Muyuan Luo, Ruibang Li, Can Department of Electrical and Electronic Engineering The University of Hong Kong Hong Kong Department of Computer Science The University of Hong Kong Hong Kong

ISBN: (纸本)9798400710773

Fast and efficient genome analysis can have a significant impact in areas such as scientific discovery and personalized medicine. Given the extensive data produced by sequencing machines, in-memory computing is considered a strong candidate to tackle the frequent data movement issue. Previous research has introduced many designs based on Content Addressable Memories (CAM), mainly optimized for tolerating edit distance;however, these systems struggle when there are a few insertion or deletion errors. This limitation presents a significant challenge for genome analysis, as current Third-Generation Sequencing still has high error rates. In this work, we introduce ShiftCAM, a time-domain Content Addressable Memory, designed to accommodate the high error rates in practical scenarios. Utilizing time-domain comparison, ShiftCAM effectively calculates the Shifted Hamming Distance to better approximate the computationally expensive edit distance. Additionally, the Modification to Accidental Match strategy specially designed for hardware implementation is introduced to eliminate accidental matches of single base pairs, further reducing false positives and improving edit distance approximation. Monte Carlo simulations based on physical ReRAM device statistical measurements and commercial PDK are also conducted to validate the robustness of the ShiftCAM design. Our experiments demonstrate that ShiftCAM can achieve an average of 2.1× (from 40.1% to 83.8%) higher F1 score in contamination analysis, 21.3% estimation error in relative abundance analysis, 51.2% reduction in cell area, 29.5× speed up, and 9.4× higher energy efficiency, compared to state-of-the-art in-memory DNA classification accelerators. © 2024 Copyright is held by the owner/author(s).

关键词： Error statistics

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2023 42nd ieee/acm international conference on computer-aided Design, ICCAD 2023 - Proceedings

2023 42nd IEEE/ACM International Conference on Computer-Aide...

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42nd ieee/acm international conference on computer-aided Design, ICCAD 2023

ISBN: (纸本)9798350315592

The proceedings contain 200 papers. The topics discussed include: Meltrix: a RRAM-based polymorphic architecture enhanced by function synthesis;PDNSig: identifying multi-tenant cloud FPGAs with power distribution network-based signatures;HAPIC: a scalable, lightweight and reactive cache for persistent-memory-based index;floorplanning for embedded multi-die interconnect bridge packages;CircuitOps: an ML infrastructure enabling generative AI for VLSI circuit optimization;FLEX : introducing flexible execution on CGRA with spatio-temporal vector dataflow;bespoke approximation of multiplication-accumulation and activation targeting printed multilayer perceptrons;side channel-assisted inference attacks on machine learning-based ECG classification;path-based processing using in-memory systolic arrays for accelerating data-intensive applications;and clock aware low power placement.

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