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Accurate, Yet Scalable: A SPICE-based Design and Optimization Framework for eNVM-based Analog In-memory Computing 24

Accurate, Yet Scalable: A SPICE-based Design and Optimizatio...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Mojahidul Ahsan, S.M. Shahriar, Muhammad Sakib Chowdhury, Mrittika Hossain, Tanvir Hasan, Md Sakib Hoque, Tamzidul Department of Electrical Engineering and Computer Science University of Kansas LawrenceKS United States Department of Electrical and Computer Engineering University of Mississippi OxfordMS United States

ISBN: (纸本)9798400710773

This paper introduces a scalable SPICE-based tool infrastructure designed to optimize analog compute-in-memory (ACIM) architectures utilizing emerging non-volatile resistive memory (eNVM) technologies. The inherent efficiency of analog eNVM crossbar arrays in performing matrix-vector multiplications significantly enhances the power, performance, and area efficiency of edge AI devices and other applications. Our framework addresses the challenges of accurately simulating ACIM architectures, which are highly susceptible to variations in process, voltage, temperature, and analog noise. The framework uses SPICE for accurate analog and mixed-signal circuit simulation. It automates the generation of SPICE-level ACIM designs for deep neural networks. Additionally, it speeds up the simulation runtime by up to 35× for large DNN models while maintaining the same SPICE-level accuracy. Moreover, it ensures simulation convergence for large netlists, facilitating SPICE simulation of large-scale eNVM crossbars that were previously impractical. We demonstrated that our framework is capable of simulating inference using netlists for MLPs with over 800,000 parameters trained on the MNIST dataset within acceptable runtime, where contemporary SPICE simulators do not even converge. We validated the simulation results in terms of inference accuracy, which shows less than a 3.8% accuracy drop compared to software-based inference results. Lastly, we demonstrated the integration of our framework with an architectural simulator, facilitating comprehensive system-level simulation. © 2024 Copyright is held by the owner/author(s).

关键词： Deep neural networks

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Optimal Layout Synthesis of Multi-Row Standard Cells for Advanced Technology Nodes 24

Optimal Layout Synthesis of Multi-Row Standard Cells for Adv...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Chung, Sehyeon Seo, Hyunbae Cho, Handong Choi, Kyumyung Kim, Taewhan Department of Electrical and Computer Engineering Seoul National University Seoul Korea Republic of

ISBN: (纸本)9798400710773

In this paper, we address three core problems in the layout synthesis of multi-row standard cells: transistor folding, row partitioning, and transistor placement. We propose a comprehensive solution to the problem of synthesizing area-optimal multi-row standard cells by seamlessly integrating transistor folding and row partitioning into the transistor placement framework. Additionally, we introduce a systematic methodology to construct a standard cell library. This methodology determines the cell types among single-row, multi-row with VDD-abut, and multi-row with VSS-abut in order to achieve an optimal trade-off between power, performance, and area (PPA) for the target design implementation. Experimental results demonstrate that for 4-routing track standard cells of the advanced technology nodes our multi-row cell generator increases the cell generation completion ratio from 72% to 100% and reduces the metal length for in-cell routing by 11.9% while maintaining comparable cell area compared to the area-minimal single-row cells. Furthermore, using our optimized cell library is able to reduce the target chip area by 4.2% and chip power by 7.0%, while all meeting timing and design rule constraints, compared to the state-of-the-art single-row standard cell library. © 2024 Copyright is held by the owner/author(s).

关键词： Boolean functions

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The Power of Graph Signal Processing for Chip Placement Acceleration 24

The Power of Graph Signal Processing for Chip Placement Acce...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Liu, Yiting Zhou, Hai Wang, Jia Yang, Fan Zeng, Xuan Shang, Li School of Computer Science Fudan University Shanghai China Department of ECE Northwestern University Evanston United States Department of ECE IIIinois Institute of Technology Chicago United States State Key Lab of ASIC & System Microelectronics Department Fudan University Shanghai China

ISBN: (纸本)9798400710773

Placement is a critical task with high computation complexity in VLSI physical design. Modern analytical placers formulate the placement objective as a nonlinear optimization task, which suffers a long iteration time. To accelerate and enhance the placement process, recent studies have turned to deep learning-based approaches, particularly leveraging graph convolution networks (GCNs). However, learning-based placers require time- and data-consuming model training due to the complexity of circuit placement that involves large-scale cells and design-specific graph statistics. This paper proposes GiFt, a parameter-free technique for accelerating placement, rooted in graph signal processing. GiFt excels at capturing multi-resolution smooth signals of circuit graphs to generate optimized placement solutions without the need for time-consuming model training, and meanwhile significantly reduces the number of iterations required by analytical placers. Experimental results show that GiFt significantly improving placement efficiency, while achieving competitive or superior performance compared to state-of-the-art placers. In particular, compared to DREAMPlace, the recently proposed GPU-accelerated analytical placer, GF-Placer improves total runtime over 45%. © 2024 Copyright is held by the owner/author(s).

关键词： Nonlinear programming

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FlexHE: a Flexible Kernel Generation Framework for Homomorphic Encryption-Based Private Inference 24

FlexHE: a Flexible Kernel Generation Framework for Homomorph...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Yu, Jiangrui Zeng, Wenxuan Xu, Tianshi Chen, Renze Liang, Yun Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China School of Software and Microelectronics Peking University Beijing China School of Computer Science Peking University Beijing China

ISBN: (纸本)9798400710773

Secure two-party computation (2PC) based on homomorphic encryption (HE) achieves formal data privacy protection and gets increasing adoption for private deep neural network (DNN) inference. As modern HE schemes usually operate on polynomials, existing works rely on manually-designed HE kernels for representative DNN operations. However, this is not only unscalable considering the diverse operator types, shapes, polynomial orders, etc, but also misses important optimization opportunities. In this paper, we introduce FlexHE, a flexible kernel generation framework to enable automatic generation and optimization of HE kernels for 2PC-based private inference. Given a high-level description of DNN operations, FlexHE can systematically define the HE kernel design space considering various optimization dimensions, including loop tiling, reordering, etc. We also analyze the communication and computation impact of different optimization dimensions for design space reduction. To search for the best kernel design, a two-level optimization problem is formulated and iteratively solved with an integer linear programming (ILP) formulation. With extensive experimental results, we not only demonstrate a better coverage of DNN operations including depth-wise Conv3D and dilated Conv3D, but also achieve more than 100×, 7.9×, and 4.2× latency reduction compared to prior-art HElayers, Cheetah, and Falcon, respectively. © 2024 Copyright is held by the owner/author(s).

关键词： Linear programming

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ADO-LLM: Analog Design Bayesian Optimization with In-Context Learning of Large Language Models 24

ADO-LLM: Analog Design Bayesian Optimization with In-Context...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Yin, Yuxuan Wang, Yu Xu, Boxun Li, Peng Department of Electronic and Computer Engineering University of California Santa BarbaraCA United States

ISBN: (纸本)9798400710773

Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine-learning-based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black-box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high-dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM’s ability to infuse domain knowledge to rapidly generate viable design points to remedy BO’s inefficiency in finding high-value design areas specifically under the limited design space coverage of the BO’s probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high-quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO’s exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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MCUBERT: Memory-Efficient BERT Inference on Commodity Microcontrollers 24

MCUBERT: Memory-Efficient BERT Inference on Commodity Microc...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Yang, Zebin Chen, Renze Wu, Taiqiang Wong, Ngai Liang, Yun Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China School of Computer Science Peking University Beijing China The University of Hong Kong Hong Kong Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (纸本)9798400710773

In this paper, we propose MCUBERT to enable language models like BERT on tiny microcontroller units (MCUs) through network and scheduling co-optimization. We observe the embedding table contributes to the major storage bottleneck for tiny BERT models. Hence, at the network level, we propose an MCU-aware two-stage neural architecture search algorithm based on clustered low-rank approximation for embedding compression. To reduce the inference memory requirements, we further propose a novel fine-grained MCU-friendly scheduling strategy. Through careful computation tiling and re-ordering as well as kernel design, we drastically increase the input sequence lengths supported on MCUs without any latency or accuracy penalty. MCUBERT reduces the parameter size of BERT-tiny and BERT-mini by 5.7× and 3.0× and the execution memory by 3.5× and 4.3×, respectively. MCUBERT also achieves 1.5× latency reduction. For the first time, MCUBERT enables lightweight BERT models on commodity MCUs and processing more than 512 tokens with less than 256KB of memory. © 2024 Copyright is held by the owner/author(s).

关键词： Microcontrollers

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Equivalence Checking for Flow-Based Computing using Iterative SAT Solving 24

Equivalence Checking for Flow-Based Computing using Iterativ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Thijssen, Sven Rashed, Muhammad Rashedul Haq Ahmed, Md Rubel Singireddy, Suraj Jha, Sumit Kumar Ewetz, Rickard Department of Electrical Engineering and Computer Science Florida Atlantic University Boca RatonFL United States Department of Computer Science and Engineering University of Texas at Arlington ArlingtonTX United States Department of Electrical and Computer Engineering University of Central Florida OrlandoFL United States Department of Electrical and Computer Engineering University of Texas at San Antonio San AntonioTX United States Knight Foundation School of Computing and Information Sciences Florida International University MiamiFL United States Department of Electrical and Computer Engineering University of Florida GainesvilleFL United States

ISBN: (纸本)9798400710773

Processing in-memory is projected to shatter the von Neumann bottleneck and enable acceleration of data-intensive applications. Flow-based computing is an efficient in-memory computing paradigm for accelerating the execution of Boolean logic. While recent synthesis algorithms can map complex functions into flow-based computing circuits, the functional correctness cannot be verified using state-of-the-art equivalence checking techniques. The challenge is that non-volatile memory devices are intrinsically bi-directional, which introduces cycles in the computational graph. These cycles break traditional equivalence checking methods that are based on SAT formulations. In this paper, we propose a framework for equivalence checking of flow-based computing circuits that is called FlowSAT. The framework captures each circuit using an undirected computational graph. The key idea of FlowSAT is to introduce helper variables, in the form of arrows, that dynamically convert the undirected graph into a directed graph. This facilitates equivalence checking to be performed using traditional SAT formulations. However, it is prohibitively expensive to ban all possible cycles using arrow variables. Therefore, we propose to eliminate cycles by iteratively adding constraints to the SAT formulation. Our experimental evaluation demonstrates that FlowSAT is up to an order of magnitude faster than state-of-the-art methods. The framework is capable of verifying all 20/20 benchmark circuits, while the previous state-of-the-art technique is only capable of verifying 12/20 circuits within a time limit of one hour. © 2024 Copyright is held by the owner/author(s).

关键词： Data flow graphs

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HeLEM-GR: Heterogeneous Global Routing with Linearized Exponential Multiplier Method 24

HeLEM-GR: Heterogeneous Global Routing with Linearized Expon...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Zhao, Chunyuan Guo, Zizheng Wang, Rui Wen, Zaiwen Liang, Yun Lin, Yibo School of Integrated Circuits Peking University China Institute of EDA Peking University China School of Mathematics Southwestern University of Finance and Economics China Beijing International Center for Mathematical Research Peking University China Beijing Advanced Innovation Center for Integrated Circuits China

ISBN: (纸本)9798400710773

Global routing (GR) plays an important role in the VLSI design flow. It not only serves as guidance for the follow-up detailed routing but also provides early design feedback for floorplanning and placement. Global routing engines are desired to provide a high-quality solution within a short time. With the design complexity growing, it becomes increasingly challenging to resolve routing overflow within affordable runtime. For example, ISPD 2024 GPU/ML-enhanced global routing contest has released large-scale industrial cases, which contain up to 50 million cells and 60 million signal nets, causing huge challenges to existing routing algorithms. In this paper, we propose HeLEM-GR, based on the linearized exponential multiplier method and heterogeneous routing kernels to achieve high-quality and ultrafast routing solutions. Our linearized exponential multiplier method can quickly reduce routing overflow. The routing process is extremely fast with GPU-enhanced massive parallelization. Experimental results demonstrate that we can achieve 4.8%-5.8% better quality scores and 1.62×-2.07× speedup compared with the top-3 winners in the ISPD 2024 contest. © 2024 Copyright is held by the owner/author(s).

关键词： Digital arithmetic

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Co-Designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment 24

Co-Designing Binarized Transformer and Hardware Accelerator ...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Ji, Yuhao Fang, Chao Ma, Shaobo Shao, Haikuo Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (纸本)9798400710773

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing model size, existing approaches suffer from algorithm-hardware mismatches with limited co-design exploration, leading to suboptimal performance on edge devices. Hence, we propose a co-design method for efficient end-to-end edge deployment of Transformers from three aspects: algorithm, hardware, and joint optimization. First, we propose BMT, a novel hardware-friendly binarized Transformer with optimized quantization methods and components, and we further enhance its model accuracy by leveraging the weighted ternary weight splitting training technique. Second, we develop a streaming processor mixed binarized Transformer accelerator, namely BAT, which is equipped with specialized units and scheduling pipelines for efficient inference of binarized Transformers. Finally, we co-optimize the algorithm and hardware through a design space exploration approach to achieve a global trade-off between accuracy, latency, and robustness for real-world deployments. Experimental results show our co-design achieves up to 2.14~49.37× throughput gains and 3.72~88.53× better energy efficiency over state-of-the-art Transformer accelerators, enabling efficient end-to-end edge deployment. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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EPipe: Pipeline Inference Framework with High-quality Offline Parallelism Planning for Heterogeneous Edge Devices 24

EPipe: Pipeline Inference Framework with High-quality Offlin...

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43rd international conference on computer-aided Design, ICCAD 2024

作者： Xiong, Yi Liu, Weihong Zhang, Rui Zu, Yulong Zhu, Zongwei Zhou, Xuehai School of Computer Science and Technology University of Science and Technology of China China Suzhou Institute for Advanced Research University of Science and Technology of China China School of Software Engineering University of Science and Technology of China China

ISBN: (纸本)9798400710773

Pipeline parallelism is essential for edge computing as it effectively consolidates the limited resources of edge devices, enabling the deployment of large Deep Neural Network (DNN) models and accelerating inference processes without compromising the performance of models. Accurate computation and communication latency estimation on heterogeneous edge devices is essential for searching for a superior parallelism plan. However, existing heterogeneous pipeline inference approaches either incur substantial resource wastage during online parallelism planning, as they utilize profiling strategies that occupy physical devices;or rely on cost models with inadequate representational capabilities, leading to inaccurate predictions, thereby harming the result of pipeline planning. This paper proposes EPipe, a novel pipeline inference framework that supports high-quality offline planning in heterogeneous edge environments. EPipe integrates two core components: the Task-Device Co-analyzer (TDC) and the Multi-pipeline Parallelism Planner (MPP). TDC utilizes an undirected connected graph to depict the compatibility of DNNs across device groups and precisely estimates inference and communication latencies through fine-grained modeling. Based on TDC, MPP utilizes a dynamic programming-based genetic algorithm to explore multi-pipeline solutions, extending beyond traditional single-pipeline methods. A comprehensive experimental evaluation on an edge testbed confirms the effectiveness of EPipe, demonstrating significant speedups in inference tasks for both task streams and single tasks. © 2024 Copyright is held by the owner/author(s).

关键词： Edge detection

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