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A technology-independent CAD tool for ESD protection device extraction - ESDExtractor 02

A technology-independent CAD tool for ESD protection device ...

引用

ieee/acm international conference on computer aided Design (ICCAD)

作者： Zhan, R.Y. Feng, H.G. Wu, Q. Chen, G. Guan, X.K. Wang, Albert Z. Dept. of Electrical Engineering Illinois Institute of Technology 3301 S. Dearborn St. Chicago IL United States

ISBN: (纸本)9780780376076

The challenges for developing an ESD (Electro-static Discharge) layout extractor originate from unconventional layout patterns of ESD protection devices, parasitic ESD device extraction and device count reduction. This paper reports a new technology-independent layout extractor, ESDExtractor, which is capable of extracting all types of ESD devices and answers the demands for ESD design verification. General methodology to extract both intentional and parasitic ESD devices, specific algorithms and implementation methods for efficiency-enhancement are presented, followed by a design example.

关键词： computer aided design

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Implicit treatment of substrate and power-ground losses in return-limited inductance extraction 02

Implicit treatment of substrate and power-ground losses in r...

引用

ieee/acm international conference on computer aided Design (ICCAD)

作者： Sitaram, Dipak Zheng, Yu Shepard, K.L. Department of Electrical Engineering Columbia University New York NY United States Cadence Design Systems New Providence NJ United States

ISBN: (纸本)9780780376076

Full-wave analysis, based on rigorous solution of the differential or integral form of Maxwell's equations, is too slow for all but the smallest designs. Traditional on-chip extraction engines are, therefore, being pushed to extract inductance and provide accurate high-frequency interconnect modelling while maintaining computational efficiency and capacity. This paper describes further accuracy-improving enhancements to the commercial full-chip RLCK extraction engine, Assura RLCX[1], based on the return-limited inductance formulation. Specifically, we incorporate substrate losses due to eddy currents and power-ground losses while, based on design-driven assumptions, avoiding explicit extraction of the power-ground and substrate. Results are validated on small testcases where comparison with full-wave solution is practical.

关键词： computer aided network analysis

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Conflict driven techniques for improving deterministic test pattern generation 02

Conflict driven techniques for improving deterministic test ...

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ieee/acm international conference on computer aided Design (ICCAD)

作者： Wang, Chen Reddy, Sudhakar M. Pomeranz, Irith Lin, Xijiang Rajski, Janusz Electrical Engineering Department University of Iowa Iowa City IA United States Computer Engineering Department University of Iowa Iowa City IA United States School of Electrical Engineering Purdue University West Lafayette IN United States Mentor Graphics Corp. Wilsonville OR United States

ISBN: (纸本)9780780376076

This work presents several new techniques for enhancing the performance of deterministic test pattern generation for VLSI circuits. The techniques introduced are called dynamic decision ordering, conflict driven recursive learning and conflict learning. An important feature shared by all these techniques is that they are triggered by the occurrence of a conflict in the generation of tests. Hence, they are not active all the time nor for all the faults. This feature allows the ATPG system that uses these techniques to resolve hard-to-resolve faults with far fewer backtracks and leaves the system as efficient as before in the absence of conflicts. We have incorporated these techniques into a commercial D-algorithm based ATPG tool. The experimental results on full scan versions of ITC'99 benchmark circuits demonstrate an improvement of the ATPG system both in the number of aborted faults and in test generation time.

关键词： Integrated circuit testing

来源：评论

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Efficient instruction encoding for automatic instruction set design of configurable ASIPs 02

Efficient instruction encoding for automatic instruction set...

引用

ieee/acm international conference on computer aided Design (ICCAD)

作者： Lee, Jong-Eun Choi, Kiyoung Dutt, Nikil Center for Embedded Computer Systems Univ. of California Irvine Irvine CA 92697 United States School of EECS Seoul National University Seoul 151-742 Korea Republic of

ISBN: (纸本)9780780376076

Application-specific instructions can significantly improve the performance, energy, and code size of configurable processors. A common approach used in the design of such instructions is to convert application-specific operation patterns into new complex instructions. However, processors with a fixed instruction bitwidth cannot accommodate all the potentially interesting operation patterns, due to the limited code space afforded by the fixed instruction bitwidth. We present a novel instruction set synthesis technique that employs an efficient instruction encoding method to achieve maximal performance improvement. We build a library of complex instructions with various encoding alternatives and select the best set of complex instructions while satisfying the instruction bitwidth constraint. We formulate the problem using integer linear programming and also present an effective heuristic algorithm. Experimental results using our technique generate instruction sets that show improvements of up to 38% over the native instruction set for several realistic benchmark applications running on a typical embedded RISC processor.

关键词： Integrated circuit layout

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Energy efficient address assignment through minimized memory row switching 02

Energy efficient address assignment through minimized memory...

引用

ieee/acm international conference on computer aided Design (ICCAD)

作者： Hettiaratchi, Sambuddhi Cheung, Peter Y.K. Clarke, Thomas J.W. Dept. of Electrical Engineering Imperial Coll. of Sci. Technol. Med. London Exhibition Road London SW7 2BT United Kingdom

ISBN: (纸本)9780780376076

Data transfer intensive applications consume a significant amount of energy in memory access. The selection of a memory location from a memory array involves driving row and column select lines. A signal transition on a row select line often consumes significantly more energy than a transition on a column select line. In order to exploit this difference in energy consumption of row and column select lines, we propose a novel address assignment methodology that aims to minimize high energy row transitions by assigning spatially and temporally local data items to the same row. The problem of energy efficient address assignment has been formulated as a multi-way graph partitioning problem and solved with a heuristic. Our experiments demonstrate that our methodology achieves row transition counts very close to the optimum and that the methodology can, for some examples, reduce row transition count by 40-70% over row major mapping. Moreover, we also demonstrate that our methodology is capable of handling access sequences with over 15 million accesses in moderate time.

关键词： Storage allocation (computer)

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A Markov chain sequence generator for power macromodeling 02

A Markov chain sequence generator for power macromodeling

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ieee/acm international conference on computer aided Design (ICCAD)

作者： Liu, Xun Papaefthymiou, Marios C. Advanced Computer Architecture Lab. Dept. of Electrical Engineering University of Michigan Ann Arbor MI 48109 United States

ISBN: (纸本)9780780376076

In this paper, we present a novel sequence generator based on a Markov chain model. Specifically, we formulate the problem of generating a sequence of vectors with given average input probability p, average transition density d, and spatial correlation s as a transition matrix computation problem, in which the matrix elements are subject to constraints derived from the specified statistics. We also give a practical heuristic that computes such a matrix and generates a sequence of l n-bit vectors in O(nl+n2) time. Derived from a strongly mixing Markov chain, our generator yields binary vector sequences with accurate statistics, high uniformly, and high randomness. Experimental results show that our sequence generator can cover more than 99% of the parameter space. Sequences of 2,000 48-bit vectors are generated in less than 0.05 seconds, with average deviations of the signal statistics p, d, and s equal to 1.6%, 1.8%, and 2.8%, respectively. Our generator enables the detailed study of power macromodeling. Using our tool and the ISCAS-85 benchmark circuits, we have assessed the sensitivity of power dissipation to the three input statistics p, d, and s. Our investigation reveals that power is most sensitive to transition density, while only occasionally exhibiting high sensitivity to signal probability and spatial correlation. Our experiments also show that input signal imbalance can cause estimation errors as high as 100% in extreme cases, although errors are usually within 25%.

关键词： Markov processes

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Shaping interconnect for uniform current density 02

Shaping interconnect for uniform current density

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ieee/acm international conference on computer aided Design (ICCAD)

作者： Shao, Muzhou Wong, D.F. Gao, Youxin Yuan, Li-Pen Cao, Huijing Department of Computer Sciences University of Texas at Austin Austin TX 78712 United States ECE Department Univ. Illinois at Urbana-Champaign Urbana IL 61801 United States Synopsys Inc. 700 E. Middlefield Rd. Mountain View CA 94043 United States Motorola Inc. Xiqing EDA No. 15 Xinghua Ave. Tianjin 30038 China

ISBN: (纸本)9780780376076

As the VLSI technology scaling down, the electromigration problem becomes one of the major concerns in high-performance IC design for both power network and signal interconnects. For a uniform width metal interconnect, the current flows through the driving point is much larger than that flows through the fan-out point since much of current bypasses to the ground through the parasitic capacitance. This causes the lifetime of driving point to be quite shorter than that of fan-out point due to electromigration. In order to avoid breakdown at the driving point, wire sizing is an effective solution. Thus we present a wire shape, of which the current density as well as the lifetime is uniform along the wire. SPICE simulation results show the uniformity of current density of this wire shape. Under the same current density bound, we demonstrate that chip area and power consumption are significantly reduced for this wire shape compared to the uniform width wire. The wire shape functions we derived are continuous. However, it is not necessary to ultra-accurately reproduce the continuous shape on the silicon, since we can round the continuous shape to the nearest available litho width and this will not degrade the uniformity of current density.

关键词： Integrated circuit layout

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Fast methods for simulation of biomolecule electrostatics 02

Fast methods for simulation of biomolecule electrostatics

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ieee/acm international conference on computer aided Design (ICCAD)

作者： Kuo, Shihhsien S. Altman, Michael D. Bardhan, Jaydeep P. Tidor, Bruce White, Jacob K. Massachusetts Inst. of Technology Dept. of Electrical Engineering 77 Massachusetts Avenue Cambridge MA 02139 United States Massachusetts Inst. of Technology Department of Chemistry 77 Massachusetts Avenue Cambridge MA 02139 United States Massachusetts Inst. of Technology Biological Engineering Division 77 Massachusetts Avenue Cambridge MA 02139 United States

ISBN: (纸本)9780780376076

computer simulation is an important tool for improving our understanding of biomolecule electrostatics, in part to aid in drug design. However, the numerical techniques used in these simulation tools do not exploit fast solver approaches widely used in analyzing integrated circuit interconnects. In this paper we describe one popular formulation used to analyze biomolecule electrostatics, present an integral formulation of the problem, and apply the precorrected-FFT method to accelerate the solution of the integral equations.

关键词： computer simulation

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Adaptive QoS control for video transmission over band-limited networks

Adaptive QoS control for video transmission over band-limite...

引用

21st Annual international conference on Consumer Electronics (ICCE)

作者： Hong, GY Fong, acm Fong, B Massey Univ IIMS Palmerston North New Zealand

ISBN: (纸本)0780373006

Consumers increasingly demand high Quality of Service (QoS) for multimedia applications. Application-layer QoS control mechanisms that do not make specific references to coding semantics tend to provide the most robust solutions for delivery of multimedia data over band-limited networks. We propose an adaptive and robust QoS algorithm for band-limited networks that integrates explicit receiver-sender rate control, rate shaping with multiple quantization parameters and adaptive FEC.

关键词： computer networks

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A new enhanced SPFD rewiring algorithm 02

A new enhanced SPFD rewiring algorithm

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ieee/acm international conference on computer aided Design (ICCAD)

作者： Cong, Jason Lin, Joey Y. Long, Wangning Computer Science Department UCLA Los Angeles CA United States

ISBN: (纸本)9780780376076

This paper presents an in-depth study of the theory and algorithms for the SPFD-based (Set of Pairs of Functions to be Distinguished) rewiring, and explores the flexibility in the SPFD computation. Our contributions are in the following two areas: (1) We present a theorem and a related algorithm for more precise characterization of feasible SPFD-based rewiring. Extensive experimental results show that for LUT-based FPGAs, the rewiring ability of our new algorithm is 70% higher than SPFD-based local rewiring algorithms (SPFD-LR) [19][21] and 18% higher than the recently developed SPFD-based global rewiring algorithm (SPFD-GR)[20]. (2) In order to achieve more rewiring ability on certain selected wires used in various optimizations, we study the impact of using different atomic SPFD pair assignment methods during the SPFD-based rewiring. We develop several heuristic atomic SPFD pair assignment methods for area or delay minimization and show that they lead to 10% more selected rewiring ability than the random (or arbitrary) assignment methods. When combining (1) and (2) together, we can achieve 38.1% higher general rewiring ability.

关键词： Logic design

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