检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

879 篇 会议
11 篇 期刊文献

馆藏范围

890 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

630 篇 工学
- 549 篇 计算机科学与技术...
- 434 篇 软件工程
- 261 篇 电气工程
- 261 篇 电子科学与技术（可...
- 78 篇 机械工程
- 48 篇 控制科学与工程
- 35 篇 信息与通信工程
- 31 篇 动力工程及工程热...
- 15 篇 材料科学与工程（可...
- 14 篇 冶金工程
- 14 篇 生物工程
- 11 篇 生物医学工程（可授...
- 10 篇 仪器科学与技术
- 10 篇 化学工程与技术
- 8 篇 建筑学
- 6 篇 光学工程
- 5 篇 力学（可授工学、理...
- 5 篇 土木工程
283 篇 理学
- 240 篇 数学
- 47 篇 物理学
- 38 篇 统计学（可授理学、...
- 16 篇 系统科学
- 14 篇 化学
- 14 篇 生物学
46 篇 管理学
- 42 篇 管理科学与工程(可...
- 17 篇 工商管理
- 4 篇 图书情报与档案管...
11 篇 法学
- 9 篇 社会学
6 篇 经济学
- 6 篇 应用经济学
3 篇 农学
2 篇 教育学
2 篇 艺术学
1 篇 医学

主题

126 篇 computer aided d...
82 篇 computer aided l...
78 篇 computer science
52 篇 computer archite...
49 篇 timing
41 篇 delay
39 篇 permission
37 篇 routing
35 篇 very large scale...
31 篇 circuit simulati...
31 篇 integrated circu...
30 篇 circuit testing
30 篇 clocks
30 篇 hardware
27 篇 computational mo...
27 篇 circuits
26 篇 circuit faults
25 篇 circuit synthesi...
25 篇 energy consumpti...
25 篇 algorithm design...

机构

16 篇 computer science...
8 篇 computer systems...
8 篇 univ calif los a...
7 篇 department of el...
6 篇 department of el...
5 篇 department of el...
5 篇 school of comput...
5 篇 beijing advanced...
5 篇 stanford univ ca...
5 篇 department of co...
5 篇 department of co...
5 篇 school of integr...
5 篇 computer science...
5 篇 department of co...
4 篇 ucla united stat...
4 篇 univ of californ...
4 篇 electrical and c...
4 篇 department of el...
4 篇 department of el...
4 篇 synopsys inc. mo...

作者

16 篇 cong jason
14 篇 m. potkonjak
9 篇 wong d.f.
9 篇 m. sarrafzadeh
8 篇 j. cong
8 篇 d.f. wong
7 篇 koh cheng-kok
7 篇 c.l. liu
7 篇 cheng chung-kuan
7 篇 lim sung kyu
6 篇 kahng andrew b.
6 篇 anon
6 篇 wong martin d.f.
6 篇 sarrafzadeh maji...
6 篇 d. kirovski
5 篇 li peng
5 篇 gang qu
5 篇 gajski daniel d.
5 篇 liu c.l.
5 篇 potkonjak miodra...

语言

845 篇 英文
41 篇 其他
4 篇 中文

检索条件"任意字段=IEEE/ACM International Conference on Computer Aide Digest"

共 890 条记录，以下是431-440 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Induction-based gate-level verification of multipliers

Induction-based gate-level verification of multipliers

引用

ieee international conference on computer-aided Design

作者： Ying-Tsai Chang Kwang-Ting Cheng Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

ISBN: (纸本)0780372476

We propose a method based on unrolling the inductive definition of binary number multiplication to verify gate-level implementations of multipliers. The induction steps successively reduce the size of the multiplier under verification. Through induction, the verification of an n-bit multiplier is decomposed into n equivalence checking problems. The resulting equivalence checking problems could be significantly sped up by simple structural analysis. This method could be generalized to the verification of more general arithmetic circuits and the equivalence checking of complex datapaths.

关键词： Circuits Boolean functions Polynomials Arithmetic Hardware Data structures Adders Very large scale integration Manuals Timing

来源：评论

学校读者我要写书评

暂无评论

System-level exploration for Pareto-optimal configurations in parameterized systems-on-a-chip 01

System-level exploration for Pareto-optimal configurations i...

引用

ieee international conference on computer-aided Design

作者： T. Givargis F. Vahid J. Henkel Center of Embedded Computer Systems University of California Irvine CA USA Department of Computer Science & Engineerin University of California Riverside CA USA C&C Research Laboratories Princeton NJ USA

ISBN: (纸本)9780780372498

Provides a technique for efficiently exploring the configuration space of a parameterized system-on-a-chip (SOC) architecture to find all Pareto-optimal configurations. These configurations represent the range of meaningful power and performance tradeoffs that are obtainable by adjusting parameter values for a fixed application mapped onto the SOC architecture. The approach extensively prunes the potentially large configuration space by taking advantage of parameter dependencies. The authors have successfully incorporated the technique into the parameterized SOC tuning environment (Platune) and applied it to a number of applications.

关键词： System-on-a-chip computer architecture Embedded computing Circuit simulation Embedded system Energy consumption computer science Laboratories National electric code Space exploration

来源：评论

学校读者我要写书评

暂无评论

Behavior-to-placed RTL synthesis with performance-driven placement 01

Behavior-to-placed RTL synthesis with performance-driven pla...

引用

ieee international conference on computer-aided Design

作者： Daehong Kim Jinyong Jung Sunghyun Lee Jinhwan Jeon Kiyoung Choi Electrical Engineering and Computer Science Seoul National University Seoul South Korea GCT Research Inc. Seoul South Korea

ISBN: (纸本)0780372476

Interconnect delay should be considered together with computation delay during architectural synthesis in order to achieve timing closure in deep submicrometer technology. In this paper, we propose an architectural synthesis technique for distributed-register architecture, which separates interconnect delay for data transfer from component delay for computation. The technique incorporates performance-driven placement into the architectural synthesis to minimize performance overhead due to interconnect delay. Experimental results show that our methodology achieves performance improvement of up to 60% and 22% on the average.

关键词： Delay effects Clocks Timing computer architecture Distributed computing Logic Delay estimation computer science Delay systems Inductance

来源：评论

学校读者我要写书评

暂无评论

Interconnect resource-aware placement for hierarchical FPGAs 01

Interconnect resource-aware placement for hierarchical FPGAs

引用

ieee international conference on computer-aided Design

作者： A. Singh G. Parthasarathy M. Marek-Sadowska Department of Electrical and Computer Engineering University of California Santa Barbara Santa Barbara CA USA

ISBN: (纸本)9780780372498

Utilizes Rent's rule as an empirical measure for efficient clustering and placement of circuits on hierarchical FPGAs. We show that careful matching of design complexity and architecture resources of hierarchical FPGAs can have a positive impact on the overall device area. We propose a circuit placement algorithm based on Rent's parameter and show that our clustering and placement techniques can improve the overall device routing area by as much as 21% for the same array size, when compared to a state-of-art FPGA placement and routing tool.

关键词： Field programmable gate arrays Routing Integrated circuit interconnections Logic devices Clustering algorithms Delay computer architecture Cost function Steiner trees Tree graphs

来源：评论

学校读者我要写书评

暂无评论

On the signal bounding problem in timing analysis 01

On the signal bounding problem in timing analysis

引用

ieee international conference on computer-aided Design

作者： Jin-Fuw Lee D.L. Ostapko J. Soreff C.K. Wong IBM T. J. Watson Research Center Yorktown Heights NY USA IBM Fishkill NY Dept. of Computer Science and Engineering The Chinese Univ. of Hong Kong New Territories Hong Kong

ISBN: (纸本)9780780372498

In this paper, we study the propagation of slew dependent bounding signals and the corresponding slew problem in static timing analysis. The selection of slew from the latest arriving signal, a commonly used strategy, may violate the rule of monotonic delay. Several methods for generating bounding signals to overcome this difficulty are described. The accuracy and monotonicity of each method is analyzed. These methods can be easily implemented in a static timer to improve the accuracy.

关键词： Timing Signal analysis Signal generators Circuit optimization Switches computer science Chip scale packaging Circuit simulation Propagation delay Delay lines

来源：评论

学校读者我要写书评

暂无评论

Area minimization of power distribution network using efficient nonlinear programming techniques 01

Area minimization of power distribution network using effici...

引用

ieee international conference on computer-aided Design

作者： Xiaohai Wu Xianlong Hon Yici Ca C.K. Cheng Jun Gu W. Dai Dept. Of Computer Science and Technology Tsinghua University Beijing China Tsinghua University Beijing Beijing CN Dept. Of Computer Science and Engineering Univ. Of California at San Diego La Jolla California USA Dept. Of Computer Science Hong Kong Univ. Of Science and Technology Hong Kong Hong Kong China Dept Of Computer Engineering Univ. Of California Santa Cruz California USA

This paper deals with area minimization of power distribution networks for VLSIs. A new algorithm based on efficient nonlinear programming techniques is presented to solve this problem. Experimental results prove that... 详细信息

ISBN: (纸本)9780780372498

关键词： Power systems Wire computer science Voltage Power engineering and energy Very large scale integration Circuits Constraint optimization Wiring Electromigration

来源：评论

学校读者我要写书评

暂无评论

STARS in VCC: complementing simulation with worst-case analysis 01

STARS in VCC: complementing simulation with worst-case analy...

引用

ieee international conference on computer-aided Design

作者： F. Balarin Cadence Berkeley Laboratories Berkeley CA USA

ISBN: (纸本)9780780372498

STARS is a methodology for worst-case analysis of embedded systems. STARS manipulates abstract representations of system components to obtain upper bounds on the number of various events in the system, as well as a bound on the response time. VCC is a commercial discrete event simulator, that can be used both for functional and performance verification. We describe an extension of VCC to facilitate STARS. The extension allows the user to specify abstract representations of VCC modules. These abstractions are used by STARS, but their validity can also be checked by VCC simulation. We also propose a mostly automatic procedure to generate these abstractions. Finally, we illustrate on an example how STARS can be combined with simulation to find bugs that would be hard to find by simulation alone.

关键词： Analytical models Discrete event simulation Embedded system Timing Upper bound Delay computer bugs Energy consumption Resource management Bandwidth

来源：评论

学校读者我要写书评

暂无评论

Congestion reduction during placement based on integer programming 01

Congestion reduction during placement based on integer progr...

引用

ieee international conference on computer-aided Design

作者： Xiaojian Yang R. Kastner M. Sarrafzadeh Computer Science Department University of California Los Angeles CA USA Computer Science Department University of California Los Angeles CA

ISBN: (纸本)9780780372498

This paper presents a novel method to reduce routing congestion during placement stage. The proposed approach is used as a post-processing step in placement. Congestion reduction is based on local improvement on the existing layout. However, the approach has a global view of the congestion over the entire design. It uses integer linear programming (ILP) to formulate the conflicts between multiple congested regions, and performs local improvement according to the solution of ILP. Experiments show that the proposed approach can effectively reduce the total overflow of global routing result. The short running time of the algorithm indicates good scalability on large designs.

关键词： Linear programming Routing Length measurement Velocity measurement Wire computer science Integer linear programming Scalability Algorithm design and analysis Very large scale integration

来源：评论

学校读者我要写书评

暂无评论

Symbolic algebra and timing driven data-flow synthesis 01

Symbolic algebra and timing driven data-flow synthesis

引用

ieee international conference on computer-aided Design

作者： A. Peymandoust G. De Micheli Computer Systems Laboratory University of Stanford Stanford CA USA

ISBN: (纸本)9780780372498

The growing market of multi-media applications has required the development of complex ASICs with significant data-path portions. Unfortunately, most high-level synthesis tools and methods cannot automatically synthesize data paths such that complex arithmetic library blocks are intelligently used. Symbolic computer algebra has been previously used to automate mapping data flow into a minimal set of complex arithmetic components. In this paper, we present extensions to the previous methods in order to find the minimal critical path delay (CPD) mapping. A new algorithm is proposed that incorporates symbolic manipulations such as tree-height-reduction, factorization, expansion, and Horner transformation. Such manipulations are used as guidelines in initial library element selection. Furthermore, we demonstrate how substitution can be used for multi-expression component sharing and critical path delay optimization.

关键词： Algebra Timing Libraries Polynomials Arithmetic Delay Guidelines High level synthesis Hardware Resource management

来源：评论

学校读者我要写书评

暂无评论

Algorithm level re-computing-a register transfer level concurrent error detection technique 01

Algorithm level re-computing-a register transfer level concu...

引用

ieee international conference on computer-aided Design

作者： K. Wu R. Karri Department of Electrical and Computer Engineering Polytechnic University Brooklyn NY USA

ISBN: (纸本)9780780372498

In this paper we propose two algorithm-level time redundancy based Concurrent Error Detection (CED) schemes that exploit diversity in a Register Transfer (RT) level implementation. RT level diversity can be achieved either by changing the operation-to-operator allocation (allocation diversity) or by shifting the operands before re-computation (data diversity). By enabling a fault to affect the normal result and the re-computed result in two different ways, RT level diversity yields good CED capability with low area overhead. We used Synopsys Behavior Compiler (BC) to implement the technique.

关键词： Redundancy Circuit faults Hardware Registers computer errors Error correction Fault detection Logic Combinational circuits Data flow computing

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共89页 << < 40 41 42 43 44 45 46 47 48 49 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：