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CALiBeR: a software pipelining algorithm for clustered embedded VLIW processors 01

CALiBeR: a software pipelining algorithm for clustered embed...

引用

ieee international conference on computer-aided Design

作者： C. Akturan M.F. Jacome Department of Electrical and Computer Engineering University of Texas Austin USA

ISBN: (纸本)9780780372498

In this paper, we describe a software pipelining framework, CALiBeR (cluster aware load balancing retiming algorithm), suitable for compilers targeting clustered embedded VLIW processors. CALiBeR can be effectively used by embedded system designers to explore different code optimization alternatives, i.e. it can assist the generation of high-quality customized retiming solutions for desired program memory size and throughput requirements, while minimizing register pressure. An extensive set of experimental results is presented, considering several representative benchmark loop kernels and a wide variety of clustered datapath configurations, demonstrating that our algorithm compares favorably with one of the best state-of-the-art algorithms, achieving up to 50% improvement in performance and up to 47% improvement in register requirements.

关键词： Embedded software Pipeline processing Clustering algorithms Software algorithms Load management VLIW Embedded system Design optimization Throughput Registers

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An assembly-level execution-time model for pipelined architectures 01

An assembly-level execution-time model for pipelined archite...

引用

ieee international conference on computer-aided Design

作者： G. Beltrame C. Brandolese W. Fornaciari F. Salice D. Sciuto V. Trianni Politecnico di Milano Milano Italy CEFRIEL Milano Italy

ISBN: (纸本)9780780372498

The aim of this work is to provide an elegant and accurate static execution timing model for 32-bit microprocessor instruction sets, covering also inter-instruction effects. Such effects depend on the processor state and the pipeline behavior, and are related to the dynamic execution of assembly code. The paper proposes a mathematical model of the delays deriving from instruction dependencies and gives a statistical characterization of such timing overheads. The model has been validated on a commercial architecture, the Intel486, by means of timing analysis of a set of benchmarks, obtaining an error within 5%. This model can be seamlessly integrated with a static energy consumption model in order to obtain precise software power and energy estimations.

关键词： Assembly Timing Energy consumption Microprocessors Mathematical model Delay Power system modeling Pipelines computer architecture Embedded software

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A simulation-based method for the verification of shared memory in multiprocessor systems 01

A simulation-based method for the verification of shared mem...

引用

ieee international conference on computer-aided Design

作者： S. Taylor C. Ramey C. Barner D. Asher Intel Corporation USA Compaq Computer Corporation USA Cavium Networks USA

ISBN: (纸本)9780780372498

As processor architectural complexity increases, greater effort must be focused on functional verification of the chip as a component of the system. Multiprocessor verification presents a particular challenge in terms of both difficulty and importance. While formal methods have made significant progress in the validation of coherence protocols, these methods are not always practical to apply to the structural implementation of a complex microprocessor. This paper describes a simulation-based approach to modeling and checking the shared-memory properties of the Alpha architecture by using a directed acyclic graph to represent memory-access orderings. The resulting tool is integrated with a simulation model of an Alpha implementation, allowing the user to verify aspects of the implementation with respect to the overall architectural specification. Both an implementation-independent and an implementation-specific version of the tool are discussed.

关键词： Multiprocessing systems Read-write memory Microprocessors Programming profession Computational modeling Random access memory Coherence Protocols Concurrent computing Law

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Crosstalk fault detection by dynamic I/sub dd/

Crosstalk fault detection by dynamic I/sub dd/

引用

ieee international conference on computer-aided Design

作者： Xiaoyun Sun Seonki Kim B. Vinnakota Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN USA

Undesired capacitive crosstalk between signals is expected to be a significant concern in deep submicron circuits. New test techniques are needed for these crosstalk faults since they may cause unacceptable performance degradation. We analyze the impact of crosstalk faults on a circuit's power dissipation. Crosstalk faults can be detected by monitoring the dynamic supply current. The test method is based on a recently developed dynamic I/sub dd/ test metric, the energy consumption ratio (ECR). ECR-based test has been shown to be effective at tolerating the impact of process variations. In this paper, we apply an ECR-based test method called ECR-VDD test to detect the crosstalk faults. The effectiveness of the method is demonstrated by simulation results.

关键词： Crosstalk Fault detection Circuit testing Circuit faults Electrical fault detection Degradation Power dissipation Monitoring Current supplies Energy consumption

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Single-pass redundancy-addition-and-removal

Single-pass redundancy-addition-and-removal

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ieee international conference on computer-aided Design

作者： Chih-Wei Chang M. Marek-Sadowska Department of Electrical and Computer Engineering University of California Santa Barbara CA USA

Redundancy-addition-and-removal is a rewiring technique which for a given target wire w/sub t/ finds a redundant alternative wire w/sub a/. Addition of w/sub a/ makes w/sub t/ redundant and hence removable without changing the overall circuit functionality. Incremental logic restructuring based on this technique has been used in many applications. However, the search for valid alternative wires requires trial-and-error redundancy testing of a potentially large set of candidate Wires. We study the fundamental theory behind this technique and propose a new reasoning scheme which directly identifies alternative wires without performing trial-and-error tests. Experimental results show up to 15 times speedup in comparison to the best techniques in literature.

关键词： Wires Timing Performance evaluation Redundancy Circuit testing Routing Engines Field programmable gate arrays Logic gates Filters

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Bus encoding to prevent crosstalk delay 01

Bus encoding to prevent crosstalk delay

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ieee international conference on computer-aided Design

作者： B. Victor K. Keutzer Department of Electrical Engineering and Computer Sciences University of California Berkeley USA

ISBN: (纸本)9780780372498

The propagation delay across long on-chip buses is increasingly becoming a limiting factor in high-speed designs. Crosstalk between adjacent wires on the bus may create a significant portion of this delay. Placing a shield wire between each signal wire alleviates the crosstalk problem but doubles the area used by the bus, an unacceptable consequence when the bus is routed using scarce top-level metal resources. Instead, we propose to employ data encoding to eliminate crosstalk delay within a bus. This paper presents a rigorous analysis of the theory behind "self-shielding codes", and gives the fundamental theoretical limits on the performance of codes with and without memory. Specifically, we find that a 32-bit bus can be encoded with 40 wires using a code with memory or 46 wires with a memoryless code, in comparison to the 63 wires required with simple shielding.

关键词： Encoding Crosstalk Wires Propagation delay Capacitance Logic Delay effects Geometry Clocks Performance analysis

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Hybrid structured clock network construction 01

Hybrid structured clock network construction

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ieee international conference on computer-aided Design

作者： Haihua Su S.S. Sapatnekar Department of Electrical and Computer Engineering University of Minnesota Minneapolis MN USA

ISBN: (纸本)9780780372498

This paper hierarchically constructs a hybrid mesh/tree clock network structure consisting of overlying zero-skew clock meshes, with underlying zero-skew clock trees originating from the mesh nodes. We propose a mesh construction procedure, which guarantees zero skew under the Elmore delay model, using a simple and efficient linear programming formulation. Buffers are inserted to reduce the transition time (or rise time). As a post-processing step, wire width optimization under an accurate higher-order delay metric is performed to further minimize the transition time and propagation delay/skew. Experimental results show that the hybrid mesh/tree construction scheme can provide smaller propagation delay and transition time than a comparable clock tree.

关键词： Clocks Delay effects Propagation delay Wire Routing Tree data structures Linear programming Very large scale integration Circuits Algorithm design and analysis

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A probabilistic constructive approach to optimization problems 01

A probabilistic constructive approach to optimization proble...

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ieee international conference on computer-aided Design

作者： J.L. Wong F. Koushanfar S. Meguerdichian M. Potkonjak EECS Department University of California Berkeley CA USA Computer Science Department University of California Los Angeles CA EECS Department University of California Berkeley CA Computer Science Department University of California Los Angeles CA USA

ISBN: (纸本)9780780372498

We propose a new optimization paradigm for solving intractable combinatorial problems. The technique, named Probabilistic Constructive (PC), combines the advantages of both constructive and probabilistic algorithms. The constructive aspect provides relatively short runtime and makes the technique amenable for the inclusion of insights through heuristic rules. The probabilistic nature facilitates a flexible trade-off between runtime and the quality of solution. In addition to presenting the generic technique, we apply it to the Maximal Independent Set problem. Extensive experimentation indicates that the new approach provides very attractive trade-offs between the quality of the solution and runtime, often outperforming the best previously published approaches.

关键词： Runtime Design automation Iterative algorithms Dynamic programming Partitioning algorithms computer science Software quality Predictive models Delay User interfaces

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Instruction generation for hybrid reconfigurable systems 01

Instruction generation for hybrid reconfigurable systems

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ieee international conference on computer-aided Design

作者： R. Kastner S. Ogrenci-Memik E. Bozorgzadeh M. Sarrafzadeh Computer Science Department University of California Los Angeles Los Angeles CA USA

ISBN: (纸本)9780780372498

We present an algorithm for simultaneous template generation and matching. The algorithm profiles the graph and iteratively contracts edges to create the templates. The algorithm is general and can be applied to any type of graph, including directed graphs and hypergraphs. We discuss how to target the algorithm towards the novel problem of instruction generation and selection for a hybrid (re)configurable systems. In particular, we target the strategically programmable system, which embeds complex computational units like ALUs, IP blocks, etc. into a configurable fabric. We argue that an essential compilation step for these systems is instruction generation, as it is needed to specify the functionality of the embedded computational units. Additionally, instruction generation can be used to create soft macros tightly sequenced pre-specified operations placed in the configurable fabric.

关键词： Hybrid power systems Fabrics Iterative algorithms Embedded computing Circuits Finite impulse response filter computer science Contracts computer aided instruction Logic

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Predicting the performance of synchronous discrete event simulation systems 01

Predicting the performance of synchronous discrete event sim...

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ieee international conference on computer-aided Design

作者： Jinsheng Xu Moon Jung Chung Department of Computer Science Michigan State University USA

ISBN: (纸本)0780372476

In this paper we propose a model to predict the performance of synchronous discrete event simulation. The model considers parameters including the number of active objects per cycle, event execution granularity and communication cost. We, derive a single formula that predicts the performance of synchronous simulation. We have benchmarked several VHDL circuits on SGI Origin 2000. The benchmark results show that the prediction model explains more than 90% of parallel simulation execution time. We also measure the effect of computation granularity over performance. The benchmark results show that although higher granularity can have better speedup because of dominance of computation over communication, the computational granularity cannot overshadow the inherent synchronization cost. This model can be used to predict the speed-up expected for synchronous simulation, and to decide whether it is worthwhile to use synchronous simulation before actually implementing it.

关键词： Discrete event simulation Predictive models Costs Computational modeling Circuit simulation Computational efficiency Parallel programming Random variables Moon computer science

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