In this paper, we report the development of the first commercial full-chip, three-dimensional, shapes-based, RLCK extraction tool, developed as part of a university-industry collaboration. The technique of return-limi...
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In this paper, we report the development of the first commercial full-chip, three-dimensional, shapes-based, RLCK extraction tool, developed as part of a university-industry collaboration. The technique of return-limited inductances is used to provide a sparse, frequency-independent inductance and resistance network with self-inductances that represent sensible 'nominal' values in the absence of mutual coupling. Mutual inductances are extracted for accurate noise analysis. The tool, Assura RLCX, exploits high-capacity scan-band techniques and disk caching for inductance extraction as an extension to Cadence's existing Assura RCX extractor.
Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed to minimize coupled switchings which do...
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Coupling effects between on-chip interconnects must be addressed in ultra deep submicron VLSI and system-on-a-chip (SoC) designs. A new low-power bus encoding scheme is proposed to minimize coupled switchings which dominate the on-chip bus power consumption. The coupling-driven bus invert method use slim encoder and decoder architecture to minimize the hardware overhead. Experimental results indicate that our encoding methods save effective switchings as much as 30% in an 8-bit bus with one-cycle redundancy.
This paper introduces the concept of abstract state exploration histories to a simulation environment, and presents a test stimulus transformation (TST) technique to improve simulation coverage. State exploration hist...
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This paper introduces the concept of abstract state exploration histories to a simulation environment, and presents a test stimulus transformation (TST) technique to improve simulation coverage. State exploration histories are adapted from reachability analysis in Formal Verification. In TST, an aggressively abstracted state exploration history is maintained during simulation. While this history is being collected, test stimuli from an existing test bench are transformed on-the-fly to explore new scenarios that are not in the history. The results showed that 3-fold increase in transition coverage for a cache coherence controller, and 10 times faster coverage convergence for a MPEG2 decoder can be achieved.
We describe a simulation-based test generation procedure for scan designs. A test sequence generated by this procedure consists of a sequence of one or more primary input vectors embedded between a scan-in operation a...
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We describe a simulation-based test generation procedure for scan designs. A test sequence generated by this procedure consists of a sequence of one or more primary input vectors embedded between a scan-in operation and a scan-out operation. We consider the set of faults that can be detected by test sequences of this form, compared to the case where scan is applied with every test vector. The proposed procedure constructs test sequences that traverse as many pairs of fault-free/faulty states as possible, and thus avoids the use of branch-and-bound test generation techniques. Additional techniques are incorporated into this basic procedure to enhance its effectiveness.
BDD-based symbolic techniques of approximate reachability analysis based on decomposing the circuit into a collection of overlapping sub-machines (also referred to as overlapping projections) have been recently propos...
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BDD-based symbolic techniques of approximate reachability analysis based on decomposing the circuit into a collection of overlapping sub-machines (also referred to as overlapping projections) have been recently proposed. Computing a superset of the reachable states in this fashion is susceptible to false negatives. Searching for real counterexamples in such an approximate space is liable to failure. In this paper, the 'hybridization effect' induced by the choice of projections is identified as the cause for the failure. A heuristic based on Hamming Distance is proposed to improve the choice of projections, that reduces the hybridization effect and facilitates either a genuine counterexample or proof of the property. The ideas are evaluated on a real large design example from the PCI Interface unit in the MAGIC chip of the Stanford FLASH Multiprocessor.
In this paper, we present an RTL delay-budgeting approach for a timing-closure-driven design method. We formulate the delay-budgeting problem into the Lagrange-Multipliers-based slack distribution problem. We present ...
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In this paper, we present an RTL delay-budgeting approach for a timing-closure-driven design method. We formulate the delay-budgeting problem into the Lagrange-Multipliers-based slack distribution problem. We present two algorithms, namely the balanced slack distribution algorithm and the AT-based (Area-Time) slack distribution algorithm, to solve the problem. We also present a timing-closure-driven design flow by integrating commercial synthesis/layout tools with the proposed algorithms. We have demonstrated the viability of the proposed RTL delay-budgeting method. The results show that without an accurate AT-characteristic projection of modules the balanced slack distribution algorithm will be a good choice for delay budgeting at RTL.
This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that captures both sizing and buffering eff...
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This paper describes an algorithm for simultaneous gate sizing and fanout optimization along the timing-critical paths in a circuit. First, a continuous-variable delay model that captures both sizing and buffering effects is presented. Next, the optimization problem is formulated as a non-convex mathematical program. To manage the problem size, only a small number of critical paths are considered simultaneously. The mathematical program is solved by a non-linear programming package. Finally, a design flow based on iterative selection and optimization of the k most critical paths in the circuit is proposed. Experimental results show that the proposed flow reduces the circuit delay by an average of 9.2% compared to conventional flows that separate gate sizing from fanout optimization.
In this paper we take a fresh look at the notion of symmetries in Boolean functions. Our studies are motivated by the fact that the classical characterization of symmetries based on invariance under variable swaps is ...
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In this paper we take a fresh look at the notion of symmetries in Boolean functions. Our studies are motivated by the fact that the classical characterization of symmetries based on invariance under variable swaps is a special case of a more general invariance based on unrestricted variable permutations. We propose a generalization of classical symmetry that allows for the simultaneous swap of ordered and unordered groups of variables, and show that it captures more of a function's invariant permutations without undue computational requirements. We apply the new symmetry definition to analyze a large set of benchmark circuits and provide extensive data showing the existence of substantial symmetries in those circuits. Specific case studies of several of these benchmarks reveal additional insights about their functional structure and how it might be related to their circuit structure.
Synchronous Data Flow (SDF) is a well-known model of computation that is widely used in the control engineering and digital signal processing domains. Existing scheduling methods are mainly static approaches that assu...
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Synchronous Data Flow (SDF) is a well-known model of computation that is widely used in the control engineering and digital signal processing domains. Existing scheduling methods are mainly static approaches that assume full knowledge of the environment, e.g. data arrival times. In a growing number of practical cases like internet multimedia applications there exists only partial knowledge of the environment, e.g. average data rates. Here, only dynamic scheduling can yield optimal results. In this paper, we propose a new dynamic scheduling method that minimizes the maximal response time of the system. It is a generalization of a deadline revision method to allow treatment of data-dependent tasks using EDF scheduling. The applicability and benefit of the new approach is shown using a real-world example.
We give an overview of a standard-cell placer Mongrel. The prototype tool adopts a middle-down methodology in which a grid is imposed over the layout area and cells are assigned to bins forming a global placement. The...
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We give an overview of a standard-cell placer Mongrel. The prototype tool adopts a middle-down methodology in which a grid is imposed over the layout area and cells are assigned to bins forming a global placement. The optimization technique applied in this phase is based on the Relaxation-Based Local Search (RBLS) framework in which a combinatorial search mechanism is driven by an analytical engine. This enables a more global view of the problem and results in complex modifications of the placement in a single search 'move'. Details of this approach including a novel placement legalization procedure are presented. When a global placement has converged, a detailed placement is formed and further optimized by the proposed optimal interleaving technique. Experimental results are presented and are quite promising, demonstrating that there is significant room for improvement in state of the art placement.
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