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Incremental CAD

Incremental CAD

引用

ieee international conference on computer-aided Design

作者： O. Coudert J. Cong S. Malik M. Sarrafzadeh Monterey Design Systems Sunnyvale CA USA Computer Science Department University of California Los Angeles CA USA Department of Electrical Engineering Princeton University Princeton NJ USA Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

Comprehensive study of incremental algorithms and solutions in the context of CAD tool development is an open area of research with a great deal of potential. Incremental algorithms for synthesis and layout are needed when design undergoes local or incremental change. Often these local changes are made to react to local change in the design, correct local errors or to make local improvements in one or more of the design quality metrics. In this paper we outline fundamental problems in incremental logic synthesis and physical design. Preliminary solutions to a subset of these problems are outlined.

关键词： Iterative algorithms Design automation Routing Timing Very large scale integration Logic Algorithm design and analysis Error correction Crosstalk Field programmable gate arrays

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Synthesis of CMOS domino circuits for charge sharing alleviation

Synthesis of CMOS domino circuits for charge sharing allevia...

引用

ieee international conference on computer-aided Design

作者： Ching-Hwa Cheng Shih-Chieh Chang Shin-De Li Wen-Ben Jone Jinn-Shyan Wang Department of Computer Science and Information Engineering National Chung Cheng University Chiayi Taiwan Department of Electrical Engineering National Chung Cheng University Chiayi Taiwan

ISBN: (纸本)0780364457

The Charge Sharing (CS) problem is one of notorious noise problems in domino circuits design and test. In this paper, this problem is thoroughly investigated by considering circuit topology and circuit function. The sensitivity of each domino gate to the CS problem is represented by the concept of CS-vulnerability. A method to derive the CS-vulnerability and the test pattern for each domino gate is suggested. We also propose a transition reordering method to dramatically reduce the CS-vulnerabilities for all domino gates, so that the CS problem can be alleviated. Simulation results demonstrate that our transistor reordering method can efficiently reduce the CS-vulnerabilities for most of domino circuits.

关键词： Circuit synthesis Circuit testing Clocks Capacitance Circuit noise Threshold voltage Inverters computer science Design engineering Circuit topology

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Verification of Delta-Sigma converters using adaptive regression modeling

Verification of Delta-Sigma converters using adaptive regres...

引用

ieee international conference on computer-aided Design

作者： Jeongjin Roh S. Seshadri J.A. Abraham Computer Engineering Research Center University of Texas Austin Austin TX USA

A new verification technique for /spl Delta//spl Sigma/ analog-to-digital converters (ADC) is proposed. The ADC is partitioned into functional blocks, and adaptive regression models for each partition are constructed using transistor-level simulation data. Non-idealities in circuit behavior are captured by the adaptive regression technique from the collected data. The algorithms have been implemented in a simulation program ARSIM (Adaptive Regression Simulator), which performs data sampling, model building, and simulation. Experimental results using ARSIM are shown on a second-order /spl Delta//spl Sigma/ modulator, and they demonstrate the effectiveness of our technique as a fast and accurate approach for verifying /spl Delta//spl Sigma/ converters.

关键词： Circuit simulation Analog-digital conversion Difference equations Analytical models Sampling methods Clocks Voltage Jacobian matrices Computational modeling Partitioning algorithms

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Generalized symmetries in Boolean functions

Generalized symmetries in Boolean functions

引用

ieee international conference on computer-aided Design

作者： V.N. Kravets K.A. Sakallah Department of Electrical Engineering and Computer Science University of Michigan Ann Arbor MI USA

In this paper we take a fresh look at the notion of symmetries in Boolean functions. Our studies are motivated by the fact that the classical characterization of symmetries based on invariance under variable swaps is a special case of a more general invariance based on unrestricted variable permutations. We propose a generalization of classical symmetry that allows for the simultaneous swap of ordered and unordered groups of variables, and show that it captures more of a function's invariant permutations without undue computational requirements. We apply the new symmetry definition to analyze a large set of benchmark circuits and provide extensive data showing the existence of substantial symmetries in those circuits. Specific case studies of several of these benchmarks reveal additional insights about their functional structure and how it might be related to their circuit structure.

关键词： Boolean functions Binary decision diagrams Network synthesis Circuits Logic Switches Libraries Design automation Contracts

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MIST: an algorithm for memory miss traffic management

MIST: an algorithm for memory miss traffic management

引用

ieee international conference on computer-aided Design

作者： P. Grun N. Dutt A. Nicolau Center for Embedded Computer Systems University of California Irvine CA USA

Cache misses represent a major bottleneck in embedded systems performance. Traditionally, compilers optimistically treated all memory accesses as cache hits, relying on the memory controller to account for longer miss delays. However, the memory controller has only a local view of the program, and is not able to efficiently hide the latency of these memory operations. Our compiler technique actively manages cache misses, and performs global miss traffic optimizations, to better hide the latency of the memory operations. Our memory-aware compiler scheduled several benchmarks on the TIC6211 processor architecture with a direct mapped cache, and generated an average of 61.6% improvement over the best schedule of the traditional (memory-transparent) optimizing compiler, demonstrating the utility of our miss traffic optimization approach.

关键词： Memory management Optimizing compilers Delay Timing Bandwidth Embedded system Processor scheduling Embedded computing Memory architecture Traffic control

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Power optimization of real-time embedded systems on variable speed processors

Power optimization of real-time embedded systems on variable...

引用

ieee international conference on computer-aided Design

作者： Youngsoo Shin Kiyoung Choi T. Sakurai Center for Collaborative Research and Institute of Industrial Science University of Tokyo Tokyo Japan School of Electrical Engineering and Computer Science Seoul National University Seoul South Korea

Power efficient design of real-time embedded systems based on programmable processors becomes more important as system functionality is increasingly realized through software. This paper presents a power optimization method for real-time embedded applications on a variable speed processor. The method combines off-line and on-line components. The off-line component determines the lowest possible maximum processor speed while guaranteeing deadlines of all tasks. The on-line component dynamically varies the processor speed or brings a processor into a power-down mode according to the status of task set in order to exploit execution time variations and idle intervals. Experimental results show that the proposed method obtains a significant power reduction across several kinds of applications.

关键词： Real time systems Embedded system Processor scheduling Energy consumption Collaborative software Optimization methods Clocks Runtime computer industry computer science

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Don't cares and multi-valued logic network minimization

Don't cares and multi-valued logic network minimization

引用

ieee international conference on computer-aided Design

作者： Yunjian Jiang R.K. Brayton Department of Electrical Engineering and Computer Sciences University of California Berkeley USA

We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and single multi-valued output. The notion of don't cares used in binary logic is generalized to multi-valued logic. It contains two types of flexibility: incomplete specification and non-determinism. We generalize the computation of observability don't cares for a multi-valued function node. Methods are given to compute (a) the maximum set of observability don't cares, and (b) the compatible set of observability don't cares for each MV-node. We give a recursive image computation to transform the don't cares into the space of local inputs of the node to be minimized. The methods are applied to some experimental multi-valued networks, and demonstrate reduction in the size of the tables that represent multi-valued logic functions.

关键词： Multivalued logic Observability computer networks Circuit synthesis Minimization methods

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Frequency domain analysis of switching noise on power supply network

Frequency domain analysis of switching noise on power supply...

引用

ieee international conference on computer-aided Design

作者： S. Zhao K. Roy Cheng-Kok Koh School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

In this paper, we propose an approach for the analysis of power supply noise in the frequency domain for power/ground (P/G) networks of tree topologies. We model the P/G network as a linear time invariant (LTI) pseudo-distributed RLC network and the gates (or cells) as time-varying current sources. Voltage fluctuation caused by the switching events is calculated based on the effective impedances seen by the corresponding current sources and the spatial correlation between the nodes of the power network. Superposition is applied to the LTI system to obtain the overall noise spectrum at any node of the power supply network. Inverse Fast Fourier Transformation (IFFT) is then performed on the frequency domain noise spectrum to obtain the time domain noise waveform. The proposed algorithm has a complexity of O(n/sup 2/). Experimental results show that our approach can produce accurate noise waveforms.

关键词： Frequency domain analysis Power supplies Circuit noise Switching circuits RLC circuits Phase noise computer networks Voltage fluctuations Very large scale integration Power systems

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Diagnosis of interconnect faults in cluster-based FPGA architectures

Diagnosis of interconnect faults in cluster-based FPGA archi...

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ieee international conference on computer-aided Design

作者： I. Harris R. Tessier Department of Electrical and Computer Engineering University of Massachusetts Amherst USA

Fault diagnosis has particular importance in the context of field programmable gate arrays (FPGAs) because faults can be avoided by reconfiguration at almost no real cost. Cluster-based FPGA architectures, in which several logic blocks are grouped together into a coarse-grained logic block, are rapidly becoming the architecture of choice for major FPGA manufacturers. The high density interconnect found within clusters greatly complicates the problem of FPGA diagnosis. We propose a technique for the testing and diagnosis of cluster-based FPGA architectures. We present a hierarchical approach to define a set of FPGA configurations in which each fault is detectable, and each fault pair is differentiable. The cornerstone of this work is the concise expression of the distinguishing conditions of each fault pair. Experimental results demonstrate that nearly 100% fault coverage and diagnostic resolution are achieved with a low number of test configurations.

关键词： Fault diagnosis Field programmable gate arrays Circuit testing Circuit faults Integrated circuit interconnections Logic devices computer architecture Costs Reconfigurable logic Fault detection

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Improving the proportion of at-speed tests in scan BIST

Improving the proportion of at-speed tests in scan BIST

引用

ieee international conference on computer-aided Design

作者： Y. Huang I. Pomeranz S.M. Reddy J. Rajski Department of Electrical & Computer Engineering University of Iowa Iowa IA USA School of Electrical & Computer Engineering Purdue University West Lafayette IN USA Mentor Graphics Corporation Wilsonville OR USA

A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e., at the normal circuit clock speed. The objectives set for choosing the lengths of the functional sequences are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The experimental results presented demonstrate that compared to earlier methods, the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

关键词： Built-in self-test Clocks Circuit testing Frequency Circuit faults Sequential circuits Power dissipation Benchmark testing System testing Design optimization

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