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Don't cares and multi-valued logic network minimization

Don't cares and multi-valued logic network minimization

引用

ieee international conference on computer-aided Design

作者： Yunjian Jiang R.K. Brayton Department of Electrical Engineering and Computer Sciences University of California Berkeley USA

We address optimizing multi-valued (MV) logic functions in a multi-level combinational logic network. Each node in the network, called an MV-node, has multi-valued inputs and single multi-valued output. The notion of don't cares used in binary logic is generalized to multi-valued logic. It contains two types of flexibility: incomplete specification and non-determinism. We generalize the computation of observability don't cares for a multi-valued function node. Methods are given to compute (a) the maximum set of observability don't cares, and (b) the compatible set of observability don't cares for each MV-node. We give a recursive image computation to transform the don't cares into the space of local inputs of the node to be minimized. The methods are applied to some experimental multi-valued networks, and demonstrate reduction in the size of the tables that represent multi-valued logic functions.

关键词： Multivalued logic Observability computer networks Circuit synthesis Minimization methods

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Frequency domain analysis of switching noise on power supply network

Frequency domain analysis of switching noise on power supply...

引用

ieee international conference on computer-aided Design

作者： S. Zhao K. Roy Cheng-Kok Koh School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

In this paper, we propose an approach for the analysis of power supply noise in the frequency domain for power/ground (P/G) networks of tree topologies. We model the P/G network as a linear time invariant (LTI) pseudo-distributed RLC network and the gates (or cells) as time-varying current sources. Voltage fluctuation caused by the switching events is calculated based on the effective impedances seen by the corresponding current sources and the spatial correlation between the nodes of the power network. Superposition is applied to the LTI system to obtain the overall noise spectrum at any node of the power supply network. Inverse Fast Fourier Transformation (IFFT) is then performed on the frequency domain noise spectrum to obtain the time domain noise waveform. The proposed algorithm has a complexity of O(n/sup 2/). Experimental results show that our approach can produce accurate noise waveforms.

关键词： Frequency domain analysis Power supplies Circuit noise Switching circuits RLC circuits Phase noise computer networks Voltage fluctuations Very large scale integration Power systems

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Diagnosis of interconnect faults in cluster-based FPGA architectures

Diagnosis of interconnect faults in cluster-based FPGA archi...

引用

ieee international conference on computer-aided Design

作者： I. Harris R. Tessier Department of Electrical and Computer Engineering University of Massachusetts Amherst USA

Fault diagnosis has particular importance in the context of field programmable gate arrays (FPGAs) because faults can be avoided by reconfiguration at almost no real cost. Cluster-based FPGA architectures, in which several logic blocks are grouped together into a coarse-grained logic block, are rapidly becoming the architecture of choice for major FPGA manufacturers. The high density interconnect found within clusters greatly complicates the problem of FPGA diagnosis. We propose a technique for the testing and diagnosis of cluster-based FPGA architectures. We present a hierarchical approach to define a set of FPGA configurations in which each fault is detectable, and each fault pair is differentiable. The cornerstone of this work is the concise expression of the distinguishing conditions of each fault pair. Experimental results demonstrate that nearly 100% fault coverage and diagnostic resolution are achieved with a low number of test configurations.

关键词： Fault diagnosis Field programmable gate arrays Circuit testing Circuit faults Integrated circuit interconnections Logic devices computer architecture Costs Reconfigurable logic Fault detection

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Improving the proportion of at-speed tests in scan BIST

Improving the proportion of at-speed tests in scan BIST

引用

ieee international conference on computer-aided Design

作者： Y. Huang I. Pomeranz S.M. Reddy J. Rajski Department of Electrical & Computer Engineering University of Iowa Iowa IA USA School of Electrical & Computer Engineering Purdue University West Lafayette IN USA Mentor Graphics Corporation Wilsonville OR USA

A method to select the lengths of functional sequences in a BIST scheme for scan designs is proposed in this paper. A functional sequence is a sequence of primary input vectors applied when the circuit operates as a sequential circuit, without using scan. These sequences can be applied at-speed, i.e., at the normal circuit clock speed. The objectives set for choosing the lengths of the functional sequences are to increase the number of vectors applied at-speed, and to reduce the number of settings of functional sequence lengths, without compromising the fault coverage achieved. The experimental results presented demonstrate that compared to earlier methods, the proposed method achieves the above objectives while also achieving higher fault coverages for most of the benchmark circuits considered.

关键词： Built-in self-test Clocks Circuit testing Frequency Circuit faults Sequential circuits Power dissipation Benchmark testing System testing Design optimization

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Effective partition-driven placement with simultaneous level processing and global net views

Effective partition-driven placement with simultaneous level...

引用

ieee/acm international conference on computer aided Design (ICCAD)

作者： Zhong, Ke Dutt, Shantanu Univ of Illinois-Chicago Chicago United States

In this paper we take a fresh look at the partition-driven placement (PDP) paradigm for standard-cell placement for wire-length minimization. The goal is to develop several new algorithms for incorporation into a PDP framework that can rectify the well-known drawbacks of traditional PDP (increasingly localized view of nests with increasing levels of the partitioning tree, min-cut objective, inaccuracy and cost of terminal propagation (TP), irreversibility of move decisions), while preserving its considerable advantages (time efficiency, flexibility in accurately incorporating many optimization metrics, and flexibility in satisfying most constraints). We have developed several novel techniques within a PDP-based framework that yield the best wire-length results so far on all but two of the MCNC benchmark suite. Our major innovations are: (1) simultaneous level partitioning (SLP) in which we partition the entire circuit globally in every level of the partitioning tree, across the current cutline(s);(2) cell gain computation based on a global or distributed view of entire nets (thus obviating TP) and on the bounding-box (BB) minimization of nets (as opposed to mincut in prior PDP);(3) move irreversibility tackled in a post-processing phase via vertical and horizontal swaps. Empirical results indicate that our PDP algorithm SPADE (for Simultaneous level PArtitioning with Distributed [i.e., global] nEt views) provides almost 20% better wirelength results than an internal version of 'regular' PDP with min-cut based gains, 10.8% better than the previous best PDP method QUAD, 10.6% better than TimberWolf (TW) 7.0, 15.8% better than the state-of-the-art force-directed technique from U. Munich (termed FD-98 here), and 15.3% better than the multilevel placement technique Snap-On. Besides TW7.0, we are also the only ones to report results on the approximately 100K-cell circuit golem3 (12.2% better than TW7.0). Our run times are quite reasonable.

关键词： computer aided design

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Corner block list: an effective and efficient topological representation of non-slicing floorplan

Corner block list: an effective and efficient topological re...

引用

ieee international conference on computer-aided Design

作者： Xianlong Hong Gang Huang Yici Cai Jiangchun Gu Sheqin Dong Chung-Kuan Cheng Jun Gu Department of Computer Science and Technology Tsinghua University Beijing China Department of Computer Science and Engineering University of California La Jolla CA USA Department of Computer Science Science and Technology University of Hong Kong Hong Kong China

ISBN: (纸本)0780364457

In this paper, a corner block list-a new efficient topological representation for non-slicing floorplan is proposed with applications to VLSI floorplan and building block placement. Given a corner block list, it takes only linear time to construct the floorplan. Unlike the O-tree structure, which determines the exact floorplan based on given block sizes, corner block list defines the floorplan independent of the block sizes. Thus, the structure is better suited for floorplan optimization with various size configurations of each block. Based on this new structure and the simulated annealing technique, an efficient floorplan algorithm is given. Soft blocks and the aspect ratio of the chip are taken into account in the simulated annealing process. The experimental results demonstrate the algorithm is quite promising.

关键词： Very large scale integration computer science Simulated annealing Circuit simulation Binary trees Application software

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A twisted-bundle layout structure for minimizing inductive coupling noise

A twisted-bundle layout structure for minimizing inductive c...

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ieee international conference on computer-aided Design

作者： G. Zhong C.-K. Koh K. Roy School of Electrical and Computer Engineering Purdue University West Lafayette IN USA

In this paper, we propose a novel twisted-bundle layout structure for minimizing inductive coupling noise. In this structure, we create several routing regions and re-order the routing of nets in each of these routing regions. The purpose is to create complementary and opposite current loops in the twisted-bundle layout structure, such that the magnetic fluxes arising from any signal net within a twisted group cancel each other in the current loop of a net of interest. The effectiveness of the twisted-bundle structure in minimizing coupling inductance has been verified by the application of FastHenry extraction on a 16-bit bus structure. We achieve about two orders of magnitude reduction in inductive coupling. SPICE simulations also show that the 16-bit twisted-bundle bus structure is able to maintain high signal integrity at high frequency of operation.

关键词： Semiconductor device noise Inductance Crosstalk Circuit noise Routing SPICE Coupling circuits Magnetic flux Frequency Integrated circuit interconnections

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On mismatches between incremental optimizers and instance perturbations in physical design tools

On mismatches between incremental optimizers and instance pe...

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ieee international conference on computer-aided Design

作者： A.B. Kahng S. Mantik Computer Science Department University of California Los Angeles Los Angeles CA USA

The incremental, "construct by correction" design methodology has become widespread in constraint-dominated DSM design. We study the problem of ECO for physical design domains in the general context of incremental optimization. We observe that an incremental design methodology is typically built from a full optimizer that generates a solution for an initial instance, and an incremental optimizer that generates a sequence of solutions corresponding to a sequence of perturbed instances. Our hypothesis is that in practice, there can be a mismatch between the strength of the incremental optimizer and the magnitude of the perturbation between successive instances. When such a mismatch occurs, the solution quality will degrade-perhaps to the point where the incremental optimizer should be replaced by the full optimizer. We document this phenomenon for three distinct domains-partitioning, placement and routing-using leading industry and academic tools. Our experiments show that current CAD tools may not be correctly designed for ECO-dominated design processes. Thus, compatibility between optimizer and instance perturbation merits attention both as a research question and as a matter of industry design practice.

关键词： Design optimization Routing Timing computer science Design methodology Optimization methods Electronic design automation and methodology Repeaters Logic design Delay estimation

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A methodology for verifying memory access protocols in behavioral synthesis

A methodology for verifying memory access protocols in behav...

引用

ieee international conference on computer-aided Design

作者： G. Koch Taewhan Kim R. Genevriere Synopsys Inc. Mountain View CA USA Department of Electrical Engineering & Computer Science Advanced Information Technology Research Center Daejeon South Korea

Memory is one of the most important components to be optimized in the several phases of the synthesis process. In behavioral synthesis, a memory is viewed as an abstract construct which hides the detail implementations of the memory. Consequently, for a vendor's memory, behavioral synthesis should create a clean model of the memory wrapper which abstracts the properties of the memory that are required to interface to the rest of the circuit. However, this wrapping process invariably demands the verification problem of the memory access protocols in order to be safely used in behavioral synthesis environment. In this paper, we propose a systematic methodology of verifying the correctness of the memory wrapper. Specifically, we analyze the complexity of the problem, and derive an effective solution which is not only practically efficient but also highly reliable. For designers who use memories as design components in behavioral synthesis, automating our solution shortens the verification time significantly in contrast of simulating memory accesses in the context of full design, which is a quite complex and time-consuming process, especially for designs with many memory access operations.

关键词： Access protocols Wrapping Hardware design languages Testing computer science Information technology Abstracts Circuit synthesis Context modeling Process design

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Bus optimization for low-power data path synthesis based on network flow method

Bus optimization for low-power data path synthesis based on ...

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ieee international conference on computer-aided Design

作者： Sungpack Hong Taewhan Kim Department of Electrical Engineering & Computer Science Advanced Information Technology Research Center Daejeon South Korea

ISBN: (纸本)0780364457

Sub-micron feature sizes have resulted in a considerable portion of power to be dissipated on the buses, causing an increased attention on savings for power at the behavioral level and RT level of design. This paper addresses the problem of minimizing power dissipated in switching of the buses in data path synthesis. Unlike the previous approaches in which minimization of the power consumed in buses has not been considered until operation scheduling is completed, our approach integrates the bus binding problem into scheduling to exploit the impact of scheduling on reduction of power dissipated on the buses more fully and effectively. We accomplish this by formulating the problem into a flow problem in a network, and devising an efficient algorithm which iteratively finds maximum flow of minimum cost solutions in the network. Experimental results on a number of benchmark problems show that given resource and global timing constraints our designs are 22% power-efficient over the designs produced by a random-move based solution, and 18% power-efficient over the designs by a clock-step based optimal solution.

关键词： Optimization methods Network synthesis Power dissipation Scheduling Portable computers Energy consumption Timing CMOS digital integrated circuits Capacitance computer science

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