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Fast analysis and optimization of power/ground networks

Fast analysis and optimization of power/ground networks

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ieee international conference on computer-aided Design

作者： H. Su K.H. Gala S.S. Sapatnekar Department of Electrical and Computer Engineering University of Minnesota Minneapolis USA University of Minnesota Minneapolis MN US

This paper presents an efficient method for optimizing power/ground (P/G) networks by widening wires and adding decoupling capacitors (decaps). It proposes a structured skeleton that is intermediate to the conventional method that uses full meshes (which are hard to analyze efficiently), and tree-structured networks (which provide poor performance). As an example, we consider a P/G network structure modeled as an overlying mesh with underlying trees originating from the mesh, which eases the task of analysis with acceptable performance sacrifices. A fast and efficient event-driven P/G network simulator is proposed, which hierarchically simulates the P/G network with an adaptation of PRIMA to handle non-zero initial conditions. An adjoint network that incorporates the variable topology of the original P/G network, as elements switch in and out of the network, is constructed to calculate the transient adjoint sensitivity over multiple intervals. The gradients of the most critical node with respect to each wire width and decap are used by a sensitivity-based heuristic optimizer that minimizes a weighted sum of the wire and the decap area. Experimental results show that this procedure can be used to efficiently optimize large networks.

关键词： Network topology Optimization methods Performance analysis Wire Voltage Circuit topology Capacitors Skeleton Discrete event simulation Switches

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General models for optimum arbitrary-dimension FPGA switch box designs

General models for optimum arbitrary-dimension FPGA switch b...

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ieee international conference on computer-aided Design

作者： Hongbing Fan Jiping Liu Yu-Liang Wu Department of Computer Science University of Victoria Victoria BC Canada Department of Math. & Computer Sci University of Lethbridge Lethbridge Canada Department of Computer Science & Engineering Chinese University of Hong Kong New Territories Hong Kong China

ISBN: (纸本)0780364457

An FPGA switch box is said to be hyper-universal if it is routable for all possible surrounding multi-pin net topologies satisfying the routing resource constraints. It is desirable to design hyper-universal switch boxes with the minimum number of switches. A previous work, Universal Switch Module, considered such a design problem concerning 2-pin net routings around a single FPGA switch box. However, as most nets are multi-pin nets in practice, it is imperative to study the problem that involves multi-pin nets. In this paper, we provide a new view of global routings and formulate the most general k-sided switch box design problem into an optimum k-partite graph design problem. Applying a powerful decomposition theorem of global routings, we prove that, for a fixed k, the number of switches in an optimum k-sided switch box with W terminals on each side is O (W), by constructing some hyper-universal switch boxes with O(W) switches. Furthermore, we obtain optimum, hyper-universal 2-sided and 3-sided switch boxes, and propose hyper-universal 4-sided switch boxes with less than 6.7 W switches, which is very close to the lower bound 6 W obtained for pure 2-pin net models.

关键词： Switches Field programmable gate arrays Routing Wire Pins Boolean functions computer science Logic arrays Councils Topology

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Generalized FDTD-ADI: an unconditionally stable full-wave Maxwell's equations solver for VLSI interconnect modeling

Generalized FDTD-ADI: an unconditionally stable full-wave Ma...

引用

ieee international conference on computer-aided Design

作者： C.C.-P. Chen Tae-Woo Lee N. Murugesan S.C. Hagness Department of Electrical and Computer Engineering University of Wisconsin Madison Madison WI USA

The finite-difference time-domain (FDTD) method of solving the full-wave Maxwell's equations has been recently extended to provide accurate and numerically stable operation for time steps exceeding the Courant limit. The elimination of an upper bound on the size of the time step was achieved using an alternating-implicit direction (ADI) time-stepping scheme. This greatly increases the computational efficiency of the FDTD method for classes of problems where the cell size of the three-dimensional space lattice is constrained to be much smaller than the shortest wavelength in the source spectrum. One such class of problems is the analysis of highspeed VLSI interconnects where full-wave methods are often needed for the accurate analysis of parasitic electromagnetic wave phenomena. In this paper, we present an enhanced FDTD-ADI formulation which permits the modeling of realistic lossy materials such as semiconductor substrates and metal conductors as well as artificial lossy materials needed for perfectly matched layer (PML) absorbing boundary conditions. Simulations using our generalized FDTD-ADI formulation are presented to demonstrate the accuracy and extent to which the computational burden is reduced by the ADI scheme.

关键词： Finite difference methods Conducting materials Time domain analysis Electromagnetic analysis Inorganic materials Semiconductor materials Maxwell equations Upper bound Computational efficiency Lattices

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Event driven simulation without loops or conditionals

Event driven simulation without loops or conditionals

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ieee international conference on computer-aided Design

作者： P.M. Maurer Department of Computer Science & Engineering University of South Florida Tampa FL USA

The past several years have seen much research in event driven logic simulation. Various logic and delay models have been explored. Most simulation research has focused on improving simulation performance. New approaches to both compiled and event driven simulation have been explored. The internal operations of event-driven simulators can be divided into two categories, scheduling, and gate simulation. Much effort has been focused on reducing the cost of scheduling. There has also been effort to reduce the cost of gate simulation. It has also been shown that explicit computation of gate outputs is unnecessary, as long as event propagation is computed correctly. Even though research has reduced the complexity of both scheduling and gate simulation, it is still necessary to test for event propagation and cancellation, and it is necessary to perform some computations during gate simulation. This paper shows that none of these computations are necessary. Most computations are devoted to testing internal states and computing new internal states. In our technique, subroutine addresses are used to maintain states. This permits the elimination of all state-testing and state-computation code. Our technique is significantly faster than conventional event-driven simulation. Unlike earlier methods, our approach can easily be extended to any logic model or any delay model.

关键词： Discrete event simulation Object oriented modeling Computational modeling Data structures Logic Processor scheduling Testing Delay Costs Performance evaluation

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Provably good global buffering using an available buffer block plan

Provably good global buffering using an available buffer blo...

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ieee international conference on computer-aided Design

作者： F.F. Dragan A.B. Kahng I. Mandoiu S. Muddu A. Zelikovsky Department of Computer Science University of California Los Angeles Los Angeles CA USA College of Computing Georgia Institute of Technology Atlanta GA USA Silicon Graphics Inc. Mountain View CA USA Department of Computer Science Georgia State University Atlanta GA USA

To implement high-performance global interconnect without impacting the performance of existing blocks, the use of buffer blocks is increasingly popular in structured-custom and block-based ASIC/SOC methodologies. Recent works by Cong et al. (1999) and Tang and Wong (2000) give algorithms to solve the buffer block planning problem. In this paper we address the problem of how to perform buffering of global nets given an existing buffer block plan. Assuming that global nets have been already decomposed into two-pin connections, we give a provably good algorithm based on a recent approach of Garg and Konemann (1998) and Fleischer (1999). Our method routes connections using available buffer blocks, such that required upper and lower bounds on buffer intervals-as well as wirelength upper bounds per connection-are satisfied. Our model allows more than one buffer to be inserted into any given connection. In addition, our algorithm observes buffer parity constraints, i.e., it will choose to use an inverter or a buffer (=co-located pair of inverters) according to source and destination signal parity. The algorithm outperforms previous approaches and has been validated on top-level layouts extracted from a recent high-end microprocessor design.

关键词： Repeaters Inverters computer science Integrated circuit interconnections Silicon Frequency estimation Delay estimation High performance computing computer graphics Application specific integrated circuits

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A data flow fault coverage metric for validation of behavioral HDL descriptions

A data flow fault coverage metric for validation of behavior...

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ieee international conference on computer-aided Design

作者： Qiushuang Zhang I.G. Harris Department of Electrical and Computer Engineering University of Massachusetts Amherst MA USA

Behavioral HDL descriptions are commonly used to capture the high-level functionality of a hardware circuit for simulation and synthesis. The manual process of creating a behavioral description is error prone, so significant effort must be made to verify the correctness of behavioral descriptions. Simulation-based validation and formal verification are both techniques used to verify correctness. We investigate validation because formal verification techniques are frequently intractable for large designs. The first step toward a behavioral validation technique is the development of a validation fault coverage metric which can be used to evaluate the likelihood of design defect detection with a given test sequence. We propose a validation fault coverage metric which is based on an analysis of the control data flow description associated with the behavior. The proposed metric identifies a subset of paths through the data flow which must be traversed during testing to detect faults. The proposed metric is a tractable compromise between the statement coverage metric which requires only that each statement be executed, and the path coverage metric which requires that all data flow paths be executed. Data flow paths are identified based on the relative code locations of definitions and uses of variables which may be assigned incorrectly due to a design error. We propose an efficient method to compute all data flow paths which must be traversed, and we generate coverage results for several benchmark VHDL circuits for comparison to other approaches.

关键词： Hardware design languages Circuit faults Circuit simulation Formal verification Fault detection Testing Circuit synthesis Error correction Fault diagnosis Data flow computing

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Latency effects of system level power management algorithms

Latency effects of system level power management algorithms

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ieee international conference on computer-aided Design

作者： D. Ramanathan S. Irani R. Gupta Department of Information and Computer Science University of California Irvine CA USA

A power management algorithm for an embedded system reduces system level power dissipation by shutting off parts of the system when they are not being used and turning them back on when they are required. Algorithms for this problem are online in nature since they must operate without knowledge of the arrival time or service requirements of future requests. In this paper, we present online algorithms to manage power for embedded systems. We perform an empirical analysis of these algorithms and give theoretical justification for the empirical results. Effective power management strategies have an adverse impact on the latency of the system for which the strategy is designed. Typically, the more aggressive the power management scheme, the greater the increase in the latency of the system. In this paper, we prove an upper bound on the additional latency of the system introduced by power management strategies. Moreover, we show that this upper bound occurs each time the system is shutdown and hence is an important system design parameter. In addition, service time and latencies have an effect on power management strategies since they alter the length and occurrences of idle periods which. We study this phenomenon experimentally, by modeling the disk drive of a laptop computer as an embedded system. The results show that if service times of arriving requests are modeled, the relative performance of algorithms can change leading to non-adaptive algorithms performing better than adaptive ones. We compare the performance of adaptive and non-adaptive power management algorithms. In particular, our experimental results show that an "immediate" shutdown strategy that shuts down the system whenever it encounters an idle period performs surprising better than sophisticated adaptive algorithms suggested in the literature. We provide an analytical explanation for the effectiveness of power management strategies.

关键词： Delay Energy management Power system management Embedded system Upper bound Power system modeling Power dissipation Turning Performance analysis Algorithm design and analysis

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Achieving fast and exact hazard-free logic minimization of extended burst-mode gC finite state machines

Achieving fast and exact hazard-free logic minimization of e...

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ieee international conference on computer-aided Design

作者： H. Jacobson C. Myers G. Gopalakrishman Department of Computer Science University of Utah USA Department of Electrical Engineering University of Utah USA

This paper presents a new approach to two-level hazard-free logic minimization in the context of extended burst-mode finite state machine synthesis targeting generalized C-elements (gC). No currently available minimizers for literal-exact two-level hazard-free logic minimization of extended burst-mode gC controllers can handle large circuits without synthesis times ranging up over thousands of seconds. Even existing heuristic approaches take too much time when iterative exploration over a large design space is required and do not yield minimum results. The logic minimization approach presented in this paper is based on state graph exploration in conjunction with single-cube cover algorithms, an approach that has not been considered for minimization of extended burst-mode finite state machines previously. Our algorithm achieves very fast logic minimization by introducing compacted state graphs and cover tables and an efficient single-cube cover algorithm for single-output minimization. Our exact logic minimizer finds minimal number of literal solutions to all currently available benchmarks, in less than one second on a 333 MHz microprocessor-more than three orders of magnitude faster than existing literal exact methods, and over an order of magnitude faster than existing heuristic methods for the largest benchmarks. This includes a benchmark that has never been possible to solve exactly in number of literals before.

关键词： Circuit synthesis Minimization methods Automata computer science Logic circuits Space exploration Hazards Jacobian matrices Iterative methods Microprocessors

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Timing driven gate duplication: complexity issues and algorithms

Timing driven gate duplication: complexity issues and algori...

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ieee international conference on computer-aided Design

作者： A. Srivastava R. Kastner M. Sarrafzadeh Department of Electrical and Computer Engineering Northwestern University Evanston IL USA

Delay optimization is a fundamental goal in logic synthesis. This paper presents gate duplication as a strategy for performance optimization. Many timing optimization strategies have been proposed over the past few years. In the past few years, the research community has looked at gate duplication extensively as a method of reducing the cut-set of partitions. Strategies of logic duplication for cut-set minimization have been suggested. The strength of gate duplication as a cut-set minimizing strategy has been demonstrated. However applicability of this strategy in reducing the circuit delay has not been studied in detail. In this paper we prove the problem of partitioning a set of fanouts between a gate and it's replica (both gates have the same fanins) such that the required time constraint at the input pin is met, to be NP-Complete. Hence even the local optimization by gate duplication problem (formally defined later) is also NP-Complete. We then present an algorithm for gate duplication which is based on the dynamic programming approach. Since the problem of partitioning a set of fanouts between a node and it's replica is NP-Complete, we use a heuristic for making this decision which is optimal under specific conditions. We report delay improvements as high as 8% over highly optimized results generated by SIS. The rest of this paper is organized as follows. Section 2 deals with the delay model and provides basic definitions. Section 3 reviews the complexity of the global gate duplication problem. Section 4 presents the proof of NP-Completeness for the local gate duplication problem. Section 5 describes a heuristic for gate duplication in detail, followed by results in Section 6. This is followed by some observations and conclusion in Section 7.

关键词： Timing Delay Circuits Capacitance Logic Optimization Minimization Tail Partitioning algorithms Dynamic programming

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Path toward future CAD environments for MEMS

Path toward future CAD environments for MEMS

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Proceedings of the 1999 ieee/acm international conference on computer-aided Design (ICCAD-99)

作者： Fedder, Gary K. Mukherjee, Tamal Carnegie Mellon Univ Pittsburgh United States

A design technique for microelectromechanical devices and systems that are compatible with VLSI design is introduced in this paper. This micromechanical design tools are implemented in existing frameworks having links between physical form and function. The aim of this studies is to give an overview MEMS application areas, and enable CAD engineers to understand the primary issues involved in integrating MEMS design with traditional electronics design flows.

关键词： computer aided design

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