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Function inlining under code size constraints for embedded processors 99

Function inlining under code size constraints for embedded p...

引用

ieee international conference on computer-aided Design

作者： R. Leupers P. Marwedel Department of Computer Science 12 University of Dortmund Dortmund Germany

ISBN: (纸本)9780780358324

Function inlining is a compiler optimization that generally increases performance at the expense of larger code size. However, current inlining techniques do not meet the special demands in the design of embedded systems, since they are based on simple heuristics, and they generate code of unpredictable size. This paper presents a novel approach to function inlining in C compilers for embedded processors, which aims at maximum program speedup under a global limit on code size. The core of this approach is a branch-and-bound algorithm which allows one to quickly explore the large search space. In an application study, we show how this algorithm can be applied to maximize the execution speed of an application under a given code size constraint.

关键词： Embedded system Program processors Assembly Optimizing compilers Registers computer science Constraint optimization Productivity Embedded computing computer architecture

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Throughput optimization of general non-linear computations 99

Throughput optimization of general non-linear computations

引用

ieee international conference on computer-aided Design

作者： I. Hong M. Potkonjak L.M. Guerra Synopsys Inc. Mountain View CA USA Computer Science Department University of California Los Angeles CA USA

ISBN: (纸本)9780780358324

This paper addresses an optimal technique for throughput optimization of general non-linear data flow computations using a set of transformations. Throughput is widely recognized as the most important design metric of the modern DSP and communication applications. Numerous approaches have been proposed for throughput optimization, but most were restricted to limited classes of computations. They have limited effectiveness when applied to large complex non-linear DSP and communication computations. The new technique is used as an optimization engine in a divide-and-conquer global approach for throughput optimization. We demonstrate the effectiveness of the new technique on numerous real-life non-linear designs.

关键词： Throughput Digital signal processing Filters Clocks Modems Design optimization Pipeline processing computer science Data flow computing Engines

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Test scheduling for core-based systems 99

Test scheduling for core-based systems

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ieee international conference on computer-aided Design

作者： K. Chakrabarty Department of Electrical & Computer Engineering Duke University Durham NC USA

ISBN: (纸本)9780780358324

We present optimal solutions to the test scheduling problem for core-based systems. We show that test scheduling is equivalent to the m-processor open-shop scheduling problem and is therefore NP-complete. However a commonly-encountered instance of this problem (m=2) can be solved in polynomial time. For the general case (m>2), we present a mixed-integer linear programming (MILP) model for optimal scheduling and apply it to a representative core-based system using an MILP solver. We also extend the MILP model to allow optimal test set selection from a set of alternatives. Finally we present an efficient heuristic algorithm for handling larger systems for which the MILP model may be infeasible.

关键词： System testing Built-in self-test Processor scheduling Logic testing Optimal scheduling Electronic equipment testing Automatic testing Polynomials Scheduling algorithm Costs

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Probabilistic state space search 99

Probabilistic state space search

引用

ieee international conference on computer-aided Design

作者： A. Kuehlmann K.L. McMillan R.K. Brayton IBM Thomas J. Watson Research Center Yorktown Heights NY USA Cadence Design Systems Inc. Berkeley CA USA University of California Berkeley CA USA

ISBN: (纸本)9780780358324

This paper describes a probabilistic approach to state space search. The presented method applies a ranking of the design states according to their probability of reaching a given target state based on a random walk model. This ranking can be used to prioritize an explicit or partial symbolic state exploration to find a trajectory from a set of initial states to a set of target states. A symbolic technique for estimating the reachability probability is described which implements a smooth trade-off between accuracy and computing effort. The presented probabilistic state space search complements incomplete verification methods which are specialized in finding errors in large designs.

关键词： State-space methods Trajectory Hardware computer interfaces Computational modeling

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Robust optimization based backtrace method for analog circuits 99

Robust optimization based backtrace method for analog circui...

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ieee international conference on computer-aided Design

作者： A.V. Gomes A. Chatterjee School of Electrical and Computer Engineering Georgia Institute of Technology Atlanta GA USA

ISBN: (纸本)9780780358324

We propose a new robust approach to signal backtrace for efficiently testing embedded analog modules in a large system. The proposed signal backtrace method is formulated as a solution to a multi-point boundary value problem (BVP), with constraints on the output state and the input. This error constraint minimizes large spurious deviations in the input signal and the convergence problems that arise if multiple solutions exist or if the desired signal does not exist in the feasible signal space. As an additional attractive advantage, this formulation preserves the core iteration structure of a SPICE-like simulator without modifications, greatly easing implementation.

关键词： Robustness Optimization methods Analog circuits Circuit testing Space technology Electronic equipment testing Circuit faults Low pass filters Flow graphs Analog computers

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Symbolic functional and timing verification of transistor-level circuits 99

Symbolic functional and timing verification of transistor-le...

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ieee international conference on computer-aided Design

作者： C.B. McDonald R.E. Bryant Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

ISBN: (纸本)9780780358324

We introduce a new method of verifying the timing of custom CMOS circuits. Due to the exponential number of patterns required, traditional simulation methods are unable to exhaustively verify a medium-sized modern logic block. Static analysis can handle much larger circuits but is not robust with respect to variations from standard circuit structures. Our approach applies symbolic simulation to analyze a circuit over all input combinations without these limitations. We present a prototype simulator (SirSim) and experimental results. We also discuss using SirSim to verify an industrial design which previously required a special-purpose verification methodology.

关键词： Timing Circuit simulation Computational modeling Delay Discrete event simulation CMOS logic circuits Analytical models Pattern analysis Latches Robustness

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FunState-an internal design representation for codesign 99

FunState-an internal design representation for codesign

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ieee international conference on computer-aided Design

作者： L. Thiele K. Strehl D. Ziegengein R. Ernst J. Teich Computer Engineering and Networks Laboratory (TIK) Swiss Federal Institute of Technology Zurich Switzerland Institute of Computer Engineering (IDA) Technical University of Braunschweig Brunswick Germany Computer Engineering Laboratory (DATE) University of Paderborn Paderborn Germany

ISBN: (纸本)9780780358324

In this paper, an internal design model called FunState (functions driven by state machines) is presented that enables the representation of different types of system components and scheduling mechanisms using a mixture of functional programming and state machines. It is shown how properties relevant for scheduling and verification of specification models like boolean dataflow, cyclostatic dataflow, synchronous dataflow, marked graphs, and communicating state machines as well as Petri nets may be represented in the FunState model. Examples of methods suited for FunState are described, such as scheduling and verification. They are based on the representation of the model's state transitions in form of a periodic graph.

关键词： Processor scheduling computer networks Design engineering Embedded system Computational modeling Data flow computing Functional programming Petri nets Timing Embedded computing

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Optimal allocation of carry-save-adders in arithmetic optimization 99

Optimal allocation of carry-save-adders in arithmetic optimi...

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ieee international conference on computer-aided Design

作者： Junhyung Um Taewhan Kim C.L. Liu Department of Computer Science and Advanced Information Technology Research Center (AITrc) Korea Advanced Institute of Science and Technology Taejon South Korea Department of Computer Science National Tsing Hua University Hsinchu Taiwan

ISBN: (纸本)9780780358324

Carry-save-adder(CSA) is one of the most widely used schemes for fast arithmetic in industry. This paper provides a solution to the problem of finding an optimal-timing allocation of CSAs. Specifically, we present a polynomial time algorithm which finds an optimal-timing CSA allocation for a given arithmetic expression. In addition, we extend our result for CSA allocation to the problem of optimizing arithmetic expressions across the boundary of design hierarchy by introducing a new concept, called auxiliary ports. Our algorithm can be used to carry out the CSA allocation step optimally and automatically, and this can be done within the context of a standard HDL synthesis environment.

关键词： Arithmetic Delay Circuit synthesis computer science Design optimization Timing Algorithm design and analysis Adders Information technology Polynomials

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The associative-skew clock routing problem 99

The associative-skew clock routing problem

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ieee international conference on computer-aided Design

作者： Yu Chen A.B. Kahng Gang Qu A. Zelikovsky Department of Computer Science UCLA Los Angeles CA USA Department of Computer Science Georgia State University Atlanta GA USA

ISBN: (纸本)9780780358324

We introduce the associative skew clock routing problem, which seeks a clock routing tree such that zero skew is preserved only within identified groups of sinks. The associative skew problem is easier to address within current EDA frameworks than useful-skew (skew-scheduling) approaches, and defines an interesting tradeoff between the traditional zero-skew clock routing problem (one sink group) and the Steiner minimum tree problem (n sink groups). We present a set of heuristic building blocks, including an efficient and optimal method of merging two zero-skew trees such that zero skew is preserved within the sink sets of each tree. Finally, we list a number of open issues for research and practical application.

关键词： Clocks Routing Costs computer science Steiner trees Merging Circuit topology Binary search trees Electronic design automation and methodology Very large scale integration

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Buffer block planning for interconnect-driven floorplanning 99

Buffer block planning for interconnect-driven floorplanning

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ieee international conference on computer-aided Design

作者： J. Cong Tianming Kong D.Z. Pan Department of Computer Science University of California Los Angeles CA USA

ISBN: (纸本)9780780358324

We study buffer block planning for interconnect-driven floorplanning in deep submicron designs. We first introduce the concept of feasible region (FR) for buffer insertion, and derive closed-form formula for FR. We observe that the FR for a buffer is quite large in general even under fairly tight delay constraints. Therefore, FR gives us a lot of flexibility to plan for buffer locations. We then develop an effective buffer block planning (BBP) algorithm to perform buffer clustering such that the overall chip area and the buffer block number can be minimized. To the best of our knowledge, this is the first in-depth study on buffer planning for interconnect-driven floorplanning with both area and delay consideration.

关键词： Integrated circuit interconnections Wire Delay estimation Design optimization Routing computer science Clustering algorithms Very large scale integration Circuit optimization Circuit synthesis

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