检索结果-内蒙古大学图书馆

您好，读者！请登录

内蒙古大学图书馆

首页
概况
党建
资源
服务
科研支持
- 论文收录引用证明
- 科技查新
知识产权
档案馆
帮助

咨询与建议

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

您的常用邮箱：*

您的手机号码：*

问题描述：

当前已输入0个字，您还可以输入200个字

全部搜索
期刊论文
图书
学位论文
标准
纸本馆藏
外文资源发现
数据库导航
超星发现

高级检索

时间限定

出版年份：

文献类型

图书期刊文献学位论文多媒体

馆藏选择

电子馆藏纸本馆藏

核心期刊

全部期刊 SCI 收录期刊 SSCI 收录期刊 EI 收录期刊 CSCD 收录期刊 CSSCI 收录期刊

语言

中文英文

文献类型

期刊文献图书学位论文标准纸本馆藏

帮助

文字说明：

T=题名（书名、题名），A=作者（责任者），K=主题词，P=出版物名称，PU=出版社名称，O=机构（作者单位、学位授予单位、专利申请人），L=中图分类号，C=学科分类号，U=全部字段，Y=年（出版发行年、学位年度、标准发布年）

检索规则说明：

AND代表“并且”；OR代表“或者”；NOT代表“不包含”；(注意必须大写,运算符两边需空一格)

检索范例：

范例一：(K=图书馆学 OR K=情报学) AND A=范并思 AND Y=1982-2016
范例二：P=计算机应用与软件 AND (U=C++ OR U=Basic) NOT K=Visual AND Y=2011-2016

分类表

所选分类

>> <<

限定检索结果

文献类型

878 篇 会议
11 篇 期刊文献

馆藏范围

889 篇 电子文献
0 种 纸本馆藏

日期分布

学科分类号

629 篇 工学
- 548 篇 计算机科学与技术...
- 433 篇 软件工程
- 261 篇 电气工程
- 261 篇 电子科学与技术（可...
- 78 篇 机械工程
- 48 篇 控制科学与工程
- 35 篇 信息与通信工程
- 31 篇 动力工程及工程热...
- 15 篇 材料科学与工程（可...
- 14 篇 冶金工程
- 14 篇 生物工程
- 11 篇 生物医学工程（可授...
- 10 篇 仪器科学与技术
- 10 篇 化学工程与技术
- 8 篇 建筑学
- 6 篇 光学工程
- 5 篇 力学（可授工学、理...
- 5 篇 土木工程
283 篇 理学
- 240 篇 数学
- 47 篇 物理学
- 38 篇 统计学（可授理学、...
- 16 篇 系统科学
- 14 篇 化学
- 14 篇 生物学
46 篇 管理学
- 42 篇 管理科学与工程(可...
- 17 篇 工商管理
- 4 篇 图书情报与档案管...
11 篇 法学
- 9 篇 社会学
6 篇 经济学
- 6 篇 应用经济学
3 篇 农学
2 篇 教育学
2 篇 艺术学
1 篇 医学

主题

126 篇 computer aided d...
82 篇 computer aided l...
78 篇 computer science
52 篇 computer archite...
49 篇 timing
41 篇 delay
39 篇 permission
37 篇 routing
35 篇 very large scale...
31 篇 circuit simulati...
31 篇 integrated circu...
30 篇 circuit testing
30 篇 clocks
30 篇 hardware
27 篇 computational mo...
27 篇 circuits
26 篇 circuit faults
25 篇 circuit synthesi...
25 篇 energy consumpti...
25 篇 algorithm design...

机构

16 篇 computer science...
8 篇 computer systems...
8 篇 univ calif los a...
7 篇 department of el...
6 篇 department of el...
5 篇 department of el...
5 篇 school of comput...
5 篇 beijing advanced...
5 篇 stanford univ ca...
5 篇 department of co...
5 篇 department of co...
5 篇 school of integr...
5 篇 computer science...
5 篇 department of co...
4 篇 ucla united stat...
4 篇 univ of californ...
4 篇 electrical and c...
4 篇 department of el...
4 篇 department of el...
4 篇 synopsys inc. mo...

作者

16 篇 cong jason
14 篇 m. potkonjak
9 篇 wong d.f.
9 篇 m. sarrafzadeh
8 篇 j. cong
8 篇 d.f. wong
7 篇 koh cheng-kok
7 篇 c.l. liu
7 篇 cheng chung-kuan
7 篇 lim sung kyu
6 篇 kahng andrew b.
6 篇 anon
6 篇 wong martin d.f.
6 篇 sarrafzadeh maji...
6 篇 d. kirovski
5 篇 li peng
5 篇 gang qu
5 篇 gajski daniel d.
5 篇 liu c.l.
5 篇 potkonjak miodra...

语言

845 篇 英文
40 篇 其他
4 篇 中文

检索条件"任意字段=IEEE/ACM International Conference on Computer Aide Digest"

共 889 条记录，以下是621-630 订阅

全选清除本页清除全部题录导出标记到"检索档案"

详细简洁

排序：

Integrated floorplanning and interconnect planning 99

Integrated floorplanning and interconnect planning

引用

ieee international conference on computer-aided Design

作者： Hung-Ming Chen Hai Zhou F.Y. Young D.F. Wong H.H. Yang N. Sherwani Department of Computer Sciences University of Technology Austin TX USA Advanced Technology Group Synopsys Inc. USA Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong China Strategic CAD Laboratories Intel Corporation Hillsboro OR USA

ISBN: (纸本)9780780358324

VLSI fabrication has entered the deep sub-micron era and communication between different components has significantly increased. Interconnect delay has become the dominant factor in total circuit delay. As a result, it is necessary to start interconnect planning as early as possible. We propose a method to combine interconnect planning with floorplanning. Our approach is based on the Wong-Liu (1986) floorplaning algorithm. When the positions, orientations, and shapes of the cells are decided, the pin positions and routing of the interconnects are decided as well. We use a multi-stage simulated annealing approach in which different interconnect planning methods are used in different ranges of temperature to reduce running time. A temperature adjustment scheme is designed to give smooth transitions between different stages of simulated annealing. Experimental results show that our approach performs well.

关键词： Integrated circuit interconnections Routing Temperature distribution Delay Simulated annealing Cost function Fabrication Wire Very large scale integration Shape

来源：评论

学校读者我要写书评

暂无评论

Attractor-repeller approach for global placement

Attractor-repeller approach for global placement

引用

ieee international conference on computer-aided Design

作者： H. Etawil S. Areibi A. Wannelli Department of Electrical and Computer Engineering University of Waterloo Waterloo ONT Canada University of Waterloo Waterloo ON CA

Traditionally, analytic placement has used linear or quadratic wirelength objective functions. Minimizing either formulation attracts cells sharing common signals (nets) together. The result is a placement with a great deal of overlap among the cells. To reduce cell overlap, the methodology iterates between global optimization and repartitioning of the placement area. In this work, we added new attractive and repulsive forces to the traditional formulation so that overlap among cells is diminished without repartitioning the placement area. The superiority of our approach stems from the fact that our new formulations are convex and no hard constraints are required. A preliminary version of the new placement method is tested using a set of MCNC benchmarks and, on average, the new method achieved 3.96% and 7.6% reduction in wirelength and CPU time compared to TimberWolf v7.0 in the hierarchical mode.

关键词： Optimization methods Testing Very large scale integration Routing Power dissipation Analytical models Simulated annealing Field programmable gate arrays Minimization Timing

来源：评论

学校读者我要写书评

暂无评论

An efficient method for hot-spot identification in ULSI circuits 99

An efficient method for hot-spot identification in ULSI circ...

引用

ieee international conference on computer-aided Design

作者： Yi-Kan Cheng Sung-Mo Kang Semiconductor Products Sector Somerset Design Center Motorola Inc. Austin TX USA Coordinated Science Laboratory Department of Electrical and Computer Engineering University of Illinois Urbana IL USA

ISBN: (纸本)0780358325

In this paper, we present a method to efficiently identify the on-chip hot spots in ULSI circuits. A set of mathematical formulae were derived in analytical forms so that local temperature information can be fetched quickly. These formulae were based on the Green's function and error function approximation, and the resulting equations were further simplified to a tractable level by asserting different constraints. Experimental result shows that this method is able to accurately locate the hot spots with little time complexity. It is particularly useful for temperature-driven circuit macro placement in the early chip design phase, for which a large number of design iterations are needed and simulation efficiency is required.

关键词： Ultra large scale integration Circuits Temperature Electrothermal effects Computational modeling Very large scale integration Thermal conductivity Heat transfer US Department of Transportation Information analysis

来源：评论

学校读者我要写书评

暂无评论

Formal specification and verification of a dataflow processor array 99

Formal specification and verification of a dataflow processo...

引用

ieee international conference on computer-aided Design

作者： T.A. Henzinger Xiaojun Liu S. Qadeer S.K. Rajamani EECS Department University of California Berkeley CA USA

ISBN: (纸本)9780780358324

We describe the formal specification and verification of the VGI parallel DSP chip (V. Srini et al., 1998), which contains 64 compute processors with /spl sim/30 K gates in each processor. Our effort coincided with the "informal" verification stage of the chip. By interacting with the designers, we produced an abstract but executable specification of the design which embodies the programmer's view of the system. Given the size of the design, an automatic check that even one of the 64 processors satisfies its specification is well beyond the scope of current verification tools. However, the check can be decomposed using assume-guarantee reasoning. For VGI, the implementation and specification operate at different time scales: several steps of the implementation correspond to a single step in the specification. We generalized both the assume-guarantee method and our model checker MOCHA to allow compositional verification for such applications. We used our proof rule to decompose the verification problem of the VGI chip into smaller proof obligations that were discharged automatically by MOCHA. Using our formal approach, we uncovered and fixed subtle bugs that were unknown to the designers.

关键词： Formal specifications computer bugs Digital signal processing chips Process design Communication system control Latches Concurrent computing Image processing Logic gates Pipelines

来源：评论

学校读者我要写书评

暂无评论

Fault modeling and simulation for crosstalk in system-on-chip interconnects 99

Fault modeling and simulation for crosstalk in system-on-chi...

引用

ieee international conference on computer-aided Design

作者： M. Cuviello S. Dey Xiaoliang Bai Yi Zhao Department of Electrical and Computer Engineering University of California San Diego La Jolla CA USA

ISBN: (纸本)9780780358324

System-on-chips (SOCs) using ultra deep sub-micron (DSM) technologies and GHz clock frequencies have been predicted by the 1997 SIA Road Map. Recent studies, as well as experiments reported in this paper, show significant crosstalk effects in long on-chip interconnects of GHz DSM chips. Recognizing the importance of high-speed, reliable interconnects in GHz SOCs, we address in this paper the problem of testing for glitch and delay errors caused by crosstalk in buses and interconnects between components of a SOC. Since it is not possible to explicitly test for all the possible process variations and defects that can lead to crosstalk errors in SOC interconnects, we present an abstract model, Maximum Aggressor (MA) fault model, and its test requirements. The attractiveness of the model is that it can abstract crosstalk defects in interconnects with a linear number of faults, while the corresponding MA tests provide complete coverage for all level defects related to cross-coupling capacitance the interconnects. A SPICE-level fault simulation methodology is presented which allows simulation of a small subset of the potentially exponential number of defects. The simulation methodology also enables validation of the proposed fault model and the resulting test set.

关键词： Crosstalk System-on-a-chip Capacitance Integrated circuit interconnections Circuit faults Inductance Signal design Clocks Circuit testing Conductors

来源：评论

学校读者我要写书评

暂无评论

Dynamic power management using adaptive learning tree 99

Dynamic power management using adaptive learning tree

引用

ieee international conference on computer-aided Design

作者： Eui-Young Chung L. Benini G. De Micheli Computer Systems Laboratory University of Stanford Stanford CA USA Dipartimento Informatica Elettronica Sistemistica Università di Bologna Bologna Italy

ISBN: (纸本)9780780358324

Dynamic power management (DPM) is a technique to reduce the power consumption of electronic systems by selectively shutting down idle components. The quality of the shutdown control algorithm (the power management policy) mostly depends on knowledge of the user's behavior, which in many cases is initially unknown or non-stationary. For this reason, DPM policies should be capable of adapting to changes in user behavior. In this paper, we present a novel DPM scheme based on idle period clustering and adaptive learning trees. We also provide a design guide for applying our technique to components with multiple sleep states. Experimental results show that our technique outperforms other advanced DPM schemes as well as simple time-out policies. The proposed approach shows little deviation of efficiency for various workloads having different characteristics, while other policies show that their efficiency changes drastically depending on the trace data characteristics. Furthermore, experimental evidence indicates that our workload learning algorithm is stable and has fast convergence.

关键词： Energy management Power system management Power system modeling Table lookup Laboratories Energy consumption Quality management Sleep Convergence Algorithm design and analysis

来源：评论

学校读者我要写书评

暂无评论

Interconnect scaling implications for CAD 99

Interconnect scaling implications for CAD

引用

ieee international conference on computer-aided Design

作者： R. Ho K. Mai H. Kapadia M. Horowitz Computer Systems Laboratory University of Stanford Stanford CA USA

ISBN: (纸本)9780780358324

Interconnect scaling to deep submicron processes presents many challenges to today's CAD flows. A recent analysis by D. Sylvester and K. Keutzer (1998) examined the behavior of average length wires under scaling, and controversially concluded that current CAD tools are adequate for future module-level designs. We show that average length wire scaling is sensitive to the technology assumptions, although the change in their behavior is small under all reasonable scaling assumptions. However, examining only average length wires is optimistic, since long wires are the ones that primarily cause CAD tool exceptions. In a module of fixed complexity, under both optimistic and pessimistic scaling assumptions, the number of long wires will increase slowly with scaling. More importantly, as the overall die capacity grows exponentially, the number of modules and thus the total number of wires in a design will also increase exponentially. Thus, if the design team size and per-designer workload is to remain relatively constant, future CAD tools will need to handle long wires much better than current tools to reduce the percentage of wires that require designer intervention.

关键词： Wires Design automation Delay Timing Load modeling Libraries Capacitance Laboratories Application specific integrated circuits Design methodology

来源：评论

学校读者我要写书评

暂无评论

A bipartition-codec architecture to reduce power in pipelined circuits 99

A bipartition-codec architecture to reduce power in pipeline...

引用

ieee international conference on computer-aided Design

作者： Shanq-Jang Ruan Rung-Ji Shang Feipei Lai Shyh-Jong Chen Xian-Jun Huang Department of Electrical Engineering and Department of Computer Science and Information Engineering National Taiwan University Taipei Taiwan

ISBN: (纸本)0780358325

Proposes a new bipartition-codec architecture that may reduce the power consumption of pipelined circuits. We treat each output value of a pipelined circuit as one state of a finite-state machine. If the output of a pipelined circuit mainly transitions among just a few states, we can partition the combinational portion of a pipelined circuit into two blocks: the one that contains the few states of high activity is small, and the other (that contains the remainder of low activity) is large. Consequently, the state transitions are confined to the small block most of the time. Then we replace the small block with a codec circuit, which consists of an encoder and a decoder, to reduce the internal switching activity of the block. The encoder minimizes the number of bit changes during state transitions; thus, the switching which propagates into the decoder is reduced considerably. We present experimental results on several MCNC benchmarks and obtain power savings of up to 63.7% by using our new architecture.

关键词： Power dissipation Switching circuits CMOS technology Logic Clocks Pins computer architecture Energy consumption Decoding Circuit synthesis

来源：评论

学校读者我要写书评

暂无评论

RLC interconnect delay estimation via moments of amplitude and phase response 99

RLC interconnect delay estimation via moments of amplitude a...

引用

ieee international conference on computer-aided Design

作者： Xiaodong Yang W.H. Ku Chung-Kuan Cheng Department of Electrical and Computer Engineering University of California San Diego CA USA Department of Computer Science and Engineering University of California San Diego CA USA

ISBN: (纸本)9780780358324

A new category of moments-Amplitude and Phase moments (AP moments) are introduced for RLC interconnect delay estimation. We show that there are tight relationships between AP moments, circuit moments and central moments. The first order AP moment represents the Elmore delay while the higher order AP moments can be used to represent the error between the Elmore delay and the exact 50% delay from the view of gain and phase-shift variation. With the help of the physical meaning revealed by the AP moments, a closed-form 50% delay model-AP delay model is proposed for RLC interconnect delay estimation in terms of the first four AP moments. We also propose a new two-pole model (AP two-pole model) by matching the first two phase moments of the transfer function. The AP two-pole model can be used for more generally timing parameters estimation. The input signal's impact on delay estimation can be incorporated into these two delay models by simply combining the input signal's AP moments with the transfer function's AP moments. In our experiments these two models show significant accuracy improvement over the Elmore delay model.

关键词： Delay estimation RLC circuits Integrated circuit interconnections Transfer functions Timing Wires Inductance Very large scale integration Transient response Uncertainty

来源：评论

学校读者我要写书评

暂无评论

JMTP: an architecture for exploiting concurrency in embedded Java applications with real-time considerations 99

JMTP: an architecture for exploiting concurrency in embedded...

引用

ieee international conference on computer-aided Design

作者： R. Helaibel K. Olukotun Comput. Syst. Lab. Stanford Univ. CA USA Computer Systems Laboratory University of Stanford Stanford CA USA

ISBN: (纸本)9780780358324

Using Java in embedded systems is plagued by problems of limited runtime performance and unpredictable runtime behavior. The Java Multi-Threaded Processor (JMTP) provides solutions to these problems. The JMTP architecture is a single chip containing an off-the-shelf general purpose processor core coupled with an array of Java Thread Processors (JTPs). Performance can be improved using this architecture by exploiting coarse-grained parallelism in the application. These performance improvements are achieved with relatively small hardware costs. Runtime predictability is improved by implementing a subset of the Java Virtual Machine (JVM) specification in the JTP and trimming away complexity without excessively restricting the Java code a JTP can handle. Moreover the JMTP architecture incorporates hardware to adaptively manage shared JMTP resources in order to satisfy JTP thread timing constraints or provide an early warning for a timing violation. This is an important feature for applications with quality-of-service demands. In addition to the hardware architecture, we describe a software framework that analyzes a Java application for expressed and implicit coarse-grained concurrent threads to execute on JTPs. This framework identifies the optimal mapping of an application to a JMTP with an arbitrary number of JTPs. We have tested this framework on a variety of applications including IDEA encryption with different JTP configurations and confirmed that the algorithm was able to obtain desired results in each case.

关键词： Concurrent computing Java Application software Runtime Yarn Hardware computer architecture Timing Embedded system Costs

来源：评论

学校读者我要写书评

暂无评论

没有更多数据了...

全选清除本页清除全部题录导出标记到“检索档案”

共89页 << < 59 60 61 62 63 64 65 66 67 68 > >>

检索报告对象比较合并检索0

隐藏清空

合并搜索

回到顶部

执行限定条件

内容：

评分：

请选择保存的检索档案：

请选择收藏分类：

订阅名称：

通借通还

温馨提示：

图书名称：

借书校区：

取书校区：

手机号码：

邮箱地址：

一卡通帐号：

电话和邮箱必须正确填写，我们会与您联系确认。

联系人：

所在院系：

联系邮箱：

联系电话：

内蒙古自治区呼和浩特市赛罕区大学西街235号邮编: 010021

建议与咨询 留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

时间限定

文献类型

馆藏选择

核心期刊

语言

文献类型

帮助

文字说明：

检索规则说明：

检索范例：

分类表

所选分类

限定检索结果

文献类型

馆藏范围

日期分布

学科分类号

主题

机构

作者

语言

请选择保存的检索档案： 新增检索档案 确定 取消

请选择收藏分类： 新增自定义分类 确定 取消

通借通还

建议与咨询留下您的常用邮箱和电话号码，以便我们向您反馈解决方案和替代方法

请选择保存的检索档案：

请选择收藏分类：