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Architecture driven circuit partitioning

Architecture driven circuit partitioning

引用

ieee international conference on computer-aided Design

作者： Chau-Shen Chen TingTing Hwang C.L. Liu Department of Computer Science National Tsing Hua University Hsinchu Taiwan

We propose an architecture driven partitioning algorithm for netlists with multi terminal nets. Our target architecture is a multi FPGA emulation system with folded Clos network for board routing. Our goal is to minimize the number of FPGA chips used and maximize the routability. To that end, we introduce a new cost function: the average number of pseudo terminals per net in a multi way cut. Experiment result shows that our algorithm is very effective in terms of the number of chips used and the routability as compared to other methods.

关键词： Integrated circuit interconnections Routing Partitioning algorithms computer architecture Field programmable gate arrays Pins Cost function Algorithm design and analysis Permission computer science

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Signature hiding techniques for FPGA intellectual property protection

Signature hiding techniques for FPGA intellectual property p...

引用

ieee international conference on computer-aided Design

作者： J. Lach W.H. Mangione-Smith M. Potkonjak Departments of Electrical Engineering University of California Los Angeles USA Computer Science University of California Los Angeles USA

This work presents the first known attempt to leverage the unique characteristics of FPGAs to protect commercial investments in intellectual property. A watermark is applied to the physical layout of a digital circuit when it is mapped into an FPGA. This watermark uniquely identifies the circuit origin and yet is difficult to detect. While this approach imposes additional constraints, experiments involving a number of large complex designs indicate that the performance impact is small.

关键词： Field programmable gate arrays Intellectual property Protection Watermarking Table lookup Investments Circuits Reverse engineering Permission Logic arrays

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Polynomial methods for component matching and verification

Polynomial methods for component matching and verification

引用

ieee international conference on computer-aided Design

作者： J. Smith G. de Micheli Computer Systems Laboratory University of Stanford Stanford CA USA

Component reuse requires designers to determine whether or not an existing component implements desired functionality. If a common structure is used to represent components that are described at multiple levels of abstraction, comparisons between circuit specifications and a library of potential implementations can be performed quickly. A mechanism is presented for compactly specifying circuit functionality as polynomials at the word level. Polynomials can be used to represent circuits that are described at the bit level or arithmetically. Furthermore, in representing components as polynomials, differences in precision between potential implementations can be detected and quantified.

关键词： Polynomials Circuits Discrete cosine transforms Libraries Arithmetic Laboratories Frequency Encoding Automation Quantization

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Efficient encoding for exact symbolic automata-based scheduling

Efficient encoding for exact symbolic automata-based schedul...

引用

ieee international conference on computer-aided Design

作者： S. Haynal F. Brewer Department of Electrical and Computer Engineering University of California Santa Barbara USA

This paper presents an efficient encoding and automaton construction which improves performance of automata-based scheduling techniques. The encoding preserves knowledge of what operations occurred previously but excludes when they occurred, allowing greater sharing among scheduling traces. The technique inherits all of the features of BDD-based control dominated scheduling including systematic speculation. Without conventional pruning, all schedules for several large samples are quickly constructed.

关键词： Encoding Job shop scheduling Optimal scheduling High level synthesis Processor scheduling Data structures Boolean functions Automatic control History Automata

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Symbolic model checking of process networks using interval diagram techniques

Symbolic model checking of process networks using interval d...

引用

ieee international conference on computer-aided Design

作者： K. Strehl L. Thiele Computer Engineering and Networks Laboratory (TIK) Swiss Federal Institute of Technology Zurich Switzerland

In this paper, an approach to symbolic model checking of process networks is introduced. It is based on interval decision diagrams (IDDs), a representation of multi-valued functions. Compared to other model checking strategies, IDDs show some important properties that enable the verification of process networks more adequately than with conventional approaches. Additionally, applications concerning scheduling are shown. A new form of transition relation representation called interval mapping diagrams (IMDs)-and their less general version predicate action diagrams (PADs)-are explained together with the corresponding methods.

关键词： Dynamic scheduling Job shop scheduling Data structures Boolean functions computer networks Processor scheduling Formal verification System recovery Permission Network synthesis

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A quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis

A quantitative approach to development and validation of syn...

引用

ieee international conference on computer-aided Design

作者： Chunho Lee M. Potkonjak Computer Science Department University of California Los Angeles CA USA

We present a quantitative approach to development and validation of synthetic benchmarks for behavioral synthesis systems. The approach is built on the idea of quantitative benchmark selection. We briefly explain the idea and present experimental results on the quantitative selection and validation of benchmarks. We develop a synthetic design example generator which composes the behavioral level specification of a design having the properties given by a set of numerical parameters. Experimental generation and application of synthetic design examples demonstrate the effectiveness of the proposed approach and the developed algorithms.

关键词： Benchmark testing Application software Design automation Software tools Algorithm design and analysis Permission computer science Software design Software algorithms Consumer electronics

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CMOS analog circuit stack generation with matching constraints

CMOS analog circuit stack generation with matching constrain...

引用

ieee international conference on computer-aided Design

作者： R. Naiknaware T. Fiez School of Electrical Engineering and Computer Science Washington State University Pullman WA USA

An efficient CMOS transistor stack generation procedure for analog circuits is described. The matching requirements are used as the primary constraint on the analog layout, however, parasitic capacitances and area considerations are also included. A designer chosen arbitrary circuit partition from the schematic can be used to generate the corresponding layout as an optimum stack of transistors with complete intra-module connectivity. The port structures are considered as part of the module area and parasitic optimization procedure. The results are demonstrated through an example and a complete chip layout of a high-resolution delta-sigma analog-to-digital converter.

关键词： CMOS analog integrated circuits Analog circuits Permission Routing computer science Parasitic capacitance Integrated circuit yield CMOS process Capacitors Mirrors

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Tight integration of combinational verification methods

Tight integration of combinational verification methods

引用

ieee international conference on computer-aided Design

作者： J.R. Burch V. Singhal Cadence Berkeley Laboratories Berkeley CA USA

Combinational verification is an important piece of most equivalence checking tools. In the recent past, many combinational verification algorithms have appeared in the literature. Previous results show that these algorithms are able to exploit circuit similarity to successfully verify large designs. However, none of these strategies seems to work when the two input designs are not equivalent. We present our combinational verification algorithm, with evidence, that is designed to be robust for both the positive and the negative problem instances. We also show that a tight integration of different verification techniques, as opposed to a coarse integration of different algorithm, is more effective at solving hard instances.

关键词： Data structures Boolean functions Binary decision diagrams computer bugs Robustness Search engines Automatic test pattern generation Switches Circuit simulation

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Hardware/software co-synthesis with memory hierarchies

Hardware/software co-synthesis with memory hierarchies

引用

ieee international conference on computer-aided Design

作者： Yanbing Li W. Wolf Department of Electrical Engineering Princeton University Princeton NJ USA

The paper introduces the first hardware/software co-synthesis algorithm of distributed real time systems that optimizes memory hierarchy along with the rest of the architecture. Our algorithm synthesize a set of real time tasks with data dependencies onto a heterogeneous multiprocessor architecture that meets the performance constraints with minimized cost. Our algorithm chooses cache sizes and allocates tasks to caches as part of co-synthesis. Experimental results, including examples from the literature and results on an MPEG-2 encoder, show that our algorithm is efficient and compared with existing algorithms, and it can reduce the overall cost of the synthesized system.

关键词： Hardware Costs Real time systems computer architecture Software performance Application software Design optimization Space exploration Permission Embedded system

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Slicing floorplans with pre-placed modules

Slicing floorplans with pre-placed modules

引用

ieee international conference on computer-aided Design

作者： F.Y. Young D.F. Wong Department of Computer Sciences University of Texas Austin

Existing floorplanners that use slicing floorplans are efficient in runtime and yet can pack modules tightly. However, none of them can handle pre-placed modules. In this paper, we extend a well-known slicing floorplanner to handle pre-placed modules. Our main contribution is a novel shape curve computation procedure which can take the positions of the pre-placed modules into consideration. The shape curve computation procedure is used repeatedly during the floorplanning process to fully exploit the shape flexibility of the modules to give a tight packing. Experimental results show that the extended floorplanner performs very well.

关键词： Shape Runtime Permission Very large scale integration Integrated circuit interconnections Costs Art Design methodology Benchmark testing

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