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A fast, accurate, and non-statistical method for fault coverage estimation

A fast, accurate, and non-statistical method for fault cover...

引用

ieee international conference on computer-aided Design

作者： M.S. Hsiao Department of Electrical arid Computer Engineering Rutgers University Piscataway NJ USA

We present a fast, dynamic fault coverage estimation technique for sequential circuits that achieves high degrees of accuracy by significantly reducing the number of injected faults and faulty-event evaluations. Specifically, we dynamically reduce injection of two types of faults: (1) hyperactive faults that never get detected, and (2) faults whose effects never propagate to a flip-flop or primary output. The cost of fault simulation is greatly reduced as injection of most of these two types of faults is prevented. Experiments show that our technique gives very accurate estimates with frequently greater speedups than the sampling techniques for most circuits. Most significantly, the proposed technique can be combined with the sampling approach to obtain speedups equivalent of small sample sizes and retain estimation accuracy of large fault samples.

关键词： Circuit faults Fault detection Electrical fault detection Costs Circuit simulation Discrete event simulation Fault diagnosis Combinational circuits Logic

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Accurate calculation of bit-level transition activity using word-level statistics and entropy function

Accurate calculation of bit-level transition activity using ...

引用

ieee international conference on computer-aided Design

作者： E.D. Kyriakis-Bitzaros S. Nikolaidis A. Tatsaki Institute of Microelectronics National Centre for Scientific Research Attiki Greece Department of Physics University of Thessaloniki Thessaloniki Greece Silicon Graphics Computer Systems Mountain View CA USA

Accurate models for the calculation of bit level switching activity in data path operators, by combining the dual bit type model with the entropy based calculation are presented. Given the input statistics, the conditional entropy per bit is estimated by means of a sigmoidal model. A polynomial approximation to the entropy of the sign bits has been developed. Entropy and switching activity of primary inputs are used to estimate the output activity. The Triple-Bit Type (TBT) model is introduced to describe the behavior of the LSBs of the multiplier output, which do not behave as white noise. The error between the results of the proposed models and the measurements of entropy and switching activity is about 1% for signals with correlation factor less than 0.8.

关键词： Statistics Entropy Energy consumption White noise Circuits Algorithm design and analysis Power dissipation Permission Probability Microelectronics

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Intellectual property protection by watermarking combinational logic synthesis solutions

Intellectual property protection by watermarking combination...

引用

ieee international conference on computer-aided Design

作者： D. Kirovski Yean-Yow Hwang M. Potkonjak J. Cong Computer Science Department University of California Los Angeles USA

The intellectual property business model is vulnerable to a number of potentially devastating obstructions, such as misappropriation and intellectual property fraud. We propose a new method for intellectual property protection which facilitates design watermarking at the combinational logic synthesis level. We developed protocols for embedding designer- and/or tool-specific information into a logic network while performing multi-level logic minimization and technology mapping. We demonstrate that the difficulty of erasing an author's signature or finding another signature in the synthesized design can be made arbitrarily computationally difficult. We also developed a statistical method which enables us to establish the strength of the proof of authorship. The watermarking method has been tested on a standard set of real-life benchmarks where an exceptionally high probability of authorship has been achieved with a negligible overhead in solution quality.

关键词： Intellectual property Protection Watermarking Logic design Network synthesis Protocols Minimization Statistical analysis Benchmark testing Probability

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Efficient transient electrothermal simulation of CMOS VLSI circuits under electrical overstress

Efficient transient electrothermal simulation of CMOS VLSI c...

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ieee international conference on computer-aided Design

作者： Tong Li Ching-Han Tsai Sung-Mo Kang Analysis Product Division Avant Corporation Department of Electrical and Computer Engineering University of Illinois Urbana-Champaign

ISBN: (纸本)1581130082

Accurate simulation of transient device thermal behavior is essential to predict CMOS VLSI circuit failures under electrical overstress (EOS). In this paper, we present an efficient transient electrothermal simulator that is built upon a SPICE-like engine. The transient device temperature is estimated by the convolution of the device power dissipation and its thermal impulse response which can be derived an analytical solution of the heat diffusion equation. New fast thermal simulation techniques are proposed including a regionwise-exponential (RWE) approximation of thermal impulse response and recursive convolution scheme. The recursive convolution provides a significant performance improvement over the numerical convolution by orders of magnitude, making it computationally feasible to simulate CMOS circuits with many devices.

关键词： Electrothermal effects Circuit simulation Very large scale integration Convolution Computational modeling Predictive models Earth Observing System Engines Transient analysis Temperature

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Estimation of power sensitivity in sequential circuits with power macromodeling application

Estimation of power sensitivity in sequential circuits with ...

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ieee international conference on computer-aided Design

作者： Zhanping Chen K. Roy E.K.P. Chong School of Elcctricd and Computer Engineering Purdue University Lafayette IN USA

We propose a novel technique based on Markov chains to accurately estimate power sensitivities to primary inputs in CMOS sequential circuits. The power sensitivity defines the change in average power dissipation due to changes in the input signal specification. Such sensitivities are estimated as by-products of the average power estimation, leading to an efficient implementation. A key application of power sensitivities is to construct a power surface in the specification space so that power dissipation under any distribution of primary inputs can easily be obtained, thereby providing an effective power macromodel for high level power estimation. We demonstrate that such a power surface can be approximated by only a limited number of representative points. This will dramatically reduce the CPU and memory requirements. Results on a large number of benchmark circuits have verified the feasibility and accuracy of this technique.

关键词： Sequential circuits Power dissipation Probability Application software Central Processing Unit Permission Power engineering computing Power engineering and energy Portable computers Minimization

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Verification by approximate forward and backward reachability

Verification by approximate forward and backward reachabilit...

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ieee international conference on computer-aided Design

作者： S.G. Govindaraju D.L. Dill Computer Systems Laboratory University of Stanford Stanford CA USA

Approximate reachability techniques trade off accuracy for the capacity to deal with bigger designs. In this paper, we extend the idea of approximations using overlapping projections to symbolic backward reachability. This is combined with a previous method of computing overapproximate forward reachable state sets using overlapping projections. The algorithm computes a superset of the set of states that lie on a path from the initial state to a state that violates a specified invariant property. If this set is empty, there is no possibility of violating the invariant. If this set is non-empty, it may be possible to prove the existence of such a path by searching for a counter-example. A simple heuristic is given, which seems to work well in practice, for generating a counter-example path from this approximation. We evaluate these new algorithms by applying them to several control modules from the I/O unit in the Stanford FLASH Multiprocessor.

关键词： Data structures Boolean functions Algorithm design and analysis Permission Laboratories Lapping Formal verification Hardware Contracts Government

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SpC: synthesis of pointers in C application of pointer analysis to the behavioral synthesis from C

SpC: synthesis of pointers in C application of pointer analy...

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ieee international conference on computer-aided Design

作者： L. Semeria G. De Micheli Computer System Laboratory University of Stanford Stanford CA USA

As designers may model mixed software-hardware systems using a subset of C or C++, we present SpC, a solution to synthesize and optimize a C model with pointers. In hardware, a pointer is not only the address of data in memory, but it may also reference multiple variables mapped to registers, ports or wires. Pointer analysis is used to find the point-to-set of each pointer in the program. We address the problem of synthesizing and optimizing pointers to multiple variables and array elements. Temporary variables are defined to optimize loads and stores by minimizing the number of live variables. The combinational logic can also be reduced by encoding the pointer values. An implementation using the SUIF framework is presented, followed by some case studies such as the synthesis of a 2D IDCT.

关键词： Hardware design languages Application software Circuit synthesis Laboratories Design optimization Registers Wires Logic Encoding System performance

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Determination of worst-case aggressor alignment for delay calculation

Determination of worst-case aggressor alignment for delay ca...

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ieee international conference on computer-aided Design

作者： P.D. Gross R. Arunachalam K. Rajagopal L.T. Pileggi Department of Electrical and Computer Engineering Carnegie Mellon University Pittsburgh PA USA

Increases in delay due to coupling can have a dramatic impact on IC performance for deep submicron technologies. To achieve maximum performance there is a need for analyzing logic stages with large complex coupled interconnects. In timing analysis, the worst case delay of gates along a critical path must include the effect of noise due to switching of nearby aggressor gates. We propose a new waveform iteration strategy to compute the delay in the presence of coupling and to align aggressor inputs to determine the worst case victim delay. We demonstrate the application of our methodology at both the transistor level and cell level. In addition, we prove that the waveforms generated in our methodology converge under typical timing analysis conditions.

关键词： Crosstalk Capacitance Switches Timing Semiconductor device noise Permission Propagation delay Logic Delay effects Integrated circuit noise

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Formal verification of pipeline control using controlled token nets and abstract interpretation

Formal verification of pipeline control using controlled tok...

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ieee international conference on computer-aided Design

作者： Pei-Hsin Ho A.J. Isles T. Kam Strategic CAD Laboratories Intel Corporation Inc. Department of EECS University of California Berkeley USA

We present an automated formal verification method that can detect common pipeline control bugs of logic design components containing thousands of registers. The method models logic designs using controlled token nets. A controlled token net consists of: a token net that models the data flow in the datapath using token semantics; a control logic that models the control machines using traditional finite state semantics. We provide algorithms to: (1) extract a controlled token net from a logic design; (2) minimize the controlled token net; and (3) compute an abstract interpretation of the controlled token net for efficient model checking. We implemented and applied the method to 6 Intel logic design components containing up to 4500 registers and successfully detected 8 pre-silicon errata.

关键词： Formal verification Pipeline processing Automatic control computer bugs Design automation Logic design Logic testing Permission Data mining Registers

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Graph matching-based algorithms for FPGA segmentation design

Graph matching-based algorithms for FPGA segmentation design

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ieee international conference on computer-aided Design

作者： Yao-Wen Chang Jai-Ming Lin D.F. Wong Department of Computer and Information Science National Chiao Tung University Hsinchu Taiwan Department of Computer Sciences University of Texas Austin Austin TX USA

Process technology advances will soon make the one-million gate FPGA a reality. A key issue that needs to be solved for the large-scale FPGAs to realize their full potential lies in the design of their segmentation architectures. One-dimensional segmentation designs have been studied to some degree in much of the literature; most of the previously proposed methods are based on stochastic or analytical analysis. In this paper, we address a new direction for studying segmentation architectures. Our method is based on graph-theoretic formulation. We first formulate a net matching problem and present a polynomial-time optimal algorithm to solve the problem. Based on the solution to the problem, we develop an effective and efficient matching-based algorithm for FPGA segmentation designs. Experimental results show that our method significantly outperforms previous work.

关键词： Field programmable gate arrays Algorithm design and analysis Switches Routing Logic arrays Large-scale systems Permission Programmable logic arrays Information science computer architecture

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