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Power invariant vector sequence compaction

Power invariant vector sequence compaction

引用

ieee international conference on computer-aided Design

作者： A. Pinar C.L. Liu Department of Computer Science University of Illinois Urbana-Champaign Department of Computer Science Sational Tsing Hua University

Simulation-based power estimation is commonly used for its high accuracy, despite excessive computation times. Techniques have been proposed to speed it up by transforming a given sequence into a shorter one while preserving the power consumption characteristics of the original sequence. This work proposes a novel method to compact a given input vector sequence to improve on the existing techniques. We propose a graph model to transform the problem to the problem of finding a heaviest weighted trail in a directed graph. We also propose a heuristic based on min-cost flow algorithms, using the graph model. Furthermore, we show that generating multiple input sequences yields better solutions in terms of both accuracy and simulation time. Experiments showed that significant reduction in simulation times can be achieved with extremely accurate results. Experiments also showed that the generation of multiple sequences improved the results further both in terms of accuracy and simulation time.

关键词： Compaction Energy consumption Power generation Circuit simulation Combinational circuits Frequency estimation Permission computer science Design optimization Power dissipation

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A performance-driven layer assignment algorithm for multiple interconnect trees

A performance-driven layer assignment algorithm for multiple...

引用

ieee international conference on computer-aided Design

作者： P. Saxena C.L. Liu Strategic CAD Laboratories Intel Corporation Inc. Hillsboro OR USA Department of Computer Science University of Illinois Urbana-Champaign National Tsing Hua University Hsinchu Taiwan

With the advent of DSM technologies, interconnect delays increasingly overshadow the transistor delays. Furthermore, since the electrical characteristics of different layers in multilayer routing technologies vary widely, the assignment of the interconnect tree edges to specific routing layers has a large impact on the interconnect delays. Traditionally, critical global interconnect trees were routed greedily, one at a time. This caused the "good" layers to be used up largely for the first few trees, yielding poor routings for the remaining trees. Multiple passes with different tree orderings were usually used to remedy the situation, although with limited success. We propose the use of dynamically adjusted area quotas to prevent the first few trees from monopolizing the "good" layers. Our approach is independent of the routing model or the router employed, and reduces the maximum tree delays by around 15% as compared to traditional algorithms.

关键词： Delay Routing Permission Electric variables computer science Costs

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Design of experiments in BDD variable ordering: lessons learned

Design of experiments in BDD variable ordering: lessons lear...

引用

ieee international conference on computer-aided Design

作者： J.E. Harlow F. Brglez Department of Electrical & Computer Engineering Duke University Durham NC USA Department of Computer Science CBL (Collaborative Benchmarking Lab) Raleigh NC USA

Applying the design of experiments methodology to the evaluation of BDD variable ordering algorithms has yielded a number of conclusive results. The methodology relies on the equivalence classes of functionally perturbed circuits that maintain logic invariance, or are within (1, 2, ...)-minterms of the original reference circuit function, also maintaining entropy-invariance. For some of the current variable ordering algorithms and tools, the negative results include: statistically significant sensitivity to naming of variables; confirmation that a number of variable ordering algorithms are statistically equivalent to a random variable order assignment; and observation of a statistically anomalous variable ordering behavior of a well known benchmark circuit isomorphic class when analyzed under single and multiple outputs. On the positive side, the methodology supports a statistically significant merit evaluation of any newly introduced variable ordering algorithm, including the one briefly introduced in this paper.

关键词： Binary decision diagrams Circuits Algorithm design and analysis US Department of Energy Design automation Very large scale integration Permission Packaging Collaboration Design methodology

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On multilevel circuit partitioning

On multilevel circuit partitioning

引用

ieee international conference on computer-aided Design

作者： S. Wichlund E.J. Aas Alcatel Telecom Norway AS Oslo Norway Norwegian University of Science and Technology

Multilevel partitioning approaches for circuit partitioning has been shown to be powerful (J. Cong and M. Smith, 1993; C.J. Alpert et al., 1996; 1997). We improve the excellent multilevel partitioning algorithm by C.J. Alpert et al. (1997) by taking edge frequency information (G. von Laszweski, 1993) into account during coarsening/uncoarsening, and to break ties. In addition, the uncoarsening phase is guided by an adaptive scheme which adds flexibility to the number of levels in the uncoarsening phase. We apply our algorithm to 13 benchmark circuits and achieve an improvement in min-cut and average min-cut values of up to 8.6% and 34.6% respectively, compared to the method by Alpert et al., at no extra runtime. Furthermore, our algorithm provides results of very stable quality. This positions our algorithm as current state of the art in multilevel circuit partitioning.

关键词： Circuits Partitioning algorithms Clustering algorithms Permission Telecommunications Runtime Joining processes Cost function computer science Very large scale integration

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Communication synthesis for distributed embedded systems

Communication synthesis for distributed embedded systems

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ieee international conference on computer-aided Design

作者： R.B. Ortega G. Borriello Department of Computing and Software Systems University of Washington Bothell WA USA Department of Computing Science & Engineering University of Washington Seattle WA USA

Designers of distributed embedded systems face many challenges in determining the tradeoffs when defining a system architecture or retargeting an existing design. Communication synthesis, the automatic generation of the necessary software and hardware for system components to exchange data, is required to more effectively explore the design space and automate very error prone tasks. The paper examines the problem of mapping a high level specification to an arbitrary architecture that uses specific, common bus protocols for interprocessor communication. The communication model presented allows for easy retargeting to different bus topologies, protocols, and illustrates that global considerations are required to achieve a correct implementation. An algorithm is presented that partitions multihop communication timing constraints to effectively utilize the bus bandwidth along a message path. The communication synthesis tool is integrated with a system co-simulator to provide performance data for a given mapping.

关键词： Embedded system computer architecture Space exploration Protocols Communication system software Hardware Topology Partitioning algorithms Spread spectrum communication Timing

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Functional debugging of systems-on-chip

Functional debugging of systems-on-chip

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ieee international conference on computer-aided Design

作者： D. Kirovski M. Potkonjak L.M. Guerra Computer Science Department University of California Los Angeles USA Rockwell Semiconductor Systems Inc. Newport Beach USA

Due to the exponential growth of both design complexity and the number of gates per pin, functional debugging has emerged as a critical step in the development of a system-on-chip. We introduce a novel debugging approach for programmable systems-on-chip. The new method leverages the advantages of the two complementary functional execution approaches, emulation and simulation. We have developed a set of tools, transparent to both the design and debugging process, which enables the user to run long test sequences in emulation, and upon error detection, roll-back to an arbitrary instance in execution time, and switch over to simulation based debugging for full design visibility and controllability. The efficacy of the approach is dependent on the method for transferring the computation from one execution domain to another. To enable effective transfer of the computation state, we have identified a set of optimization tasks, established their computation complexity, and developed an efficient suite of optimization algorithms.

关键词： Debugging Emulation Controllability Observability Computational modeling Circuit simulation Switches Logic testing Logic arrays Permission

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Transforming control-flow intensive designs to facilitate power management

Transforming control-flow intensive designs to facilitate po...

引用

ieee international conference on computer-aided Design

作者： G. Lakshminarayana A. Raghunathan N.K. Jhat S. Dey Department of Electrical Engineering Princeton University Princeton NJ USA CCRL NEC USA Inc. Princeton NJ USA Department of Electrical and Computer Engg. University of California San Diego CA USA

We present techniques to transform scheduled descriptions of control-flow intensive (CFI) designs to facilitate power management. We investigate the factors that inhibit the application of power management in synthesized register-transfer level (RTL) implementations. Based on these insights, we present transformation techniques based on the concepts of variable protection, variable renaming and re-assignment, and limited controller state memory insertion that result in inherently power-managed architectures. Our transformation techniques can be easily used in conjunction with any existing resource sharing algorithm or in the framework of existing high-level synthesis tools. Experimental results on CFI designs indicate reductions of up to 76.6% (35.6% on average) in power consumption at area overheads not exceeding 10.1% (1.1% on average) over already power-optimized designs.

关键词： Energy management Protection Scheduling Engineering management Energy consumption Power dissipation Permission Automatic control Circuits Power engineering computing

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Word-level decision diagrams, WLCDs and division

Word-level decision diagrams, WLCDs and division

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ieee international conference on computer-aided Design

作者： C. Scholl B. Becker T.M. Weis Institute of Computer Science Albert Ludwig University Freiburg im Breisgau Germany

Several types of decision diagrams (DDs) have been proposed for the verification of integrated circuits. Recently, word-level DDs like BMDs, *BMDs, HDDs, K*BMDs and *PHDDs have been attracting more and more interest, e.g., by using *BMDs and *PHDDs it was for the first time possible to formally verify integer multipliers and floating point multipliers of "significant" bitlengths, respectively. On the other hand, it has been unknown, whether division, the operation inverse to multiplication can be efficiently represented by some type of word-level DDs. We show that the representational power of any word-level DD is too weak to efficiently represent integer division. Thus, neither a clever choice of the variable ordering, the decomposition type or the edge weights, can lead to a polynomial DD size for division. For the proof we introduce word-level linear combination diagrams (WLCDs), a DD, which may be viewed as a "generic" word-level DD. We derive an exponential lower bound on the WLCD representation size for integer dividers and show how this bound transfers to all other word-level DDs.

关键词： Data structures Boolean functions Polynomials Circuits Permission computer science Logic Adders

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Network flow based circuit partitioning for time-multiplexed FPGAs

Network flow based circuit partitioning for time-multiplexed...

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ieee international conference on computer-aided Design

作者： Huiqun Liu D.F. Wong Department of Computer Sciences University of Texas Austin TX USA

Time multiplexed FPGAs have the potential to dramatically improve logic density by time sharing logic, and have become an active research for reconfigurable computing. The partitioning problem for time multiplexed FPGAs is different from the traditional partitioning problem in that the nodes have precedence constraints among them, and the widely used iterative improvement partitioning methods such as K&L, FM (C.M. Fiduccia and R.M. Mattheyses, 1982; B.W. Kernighan and S. Lin, 1978) are no longer applicable. All later approaches (S. Trimberger, 1998; D. Chang and M. Marek-Sadowska, 1998; 1997) used list scheduling heuristics. We present a network flow based algorithm for multi way precedence constrained partitioning, which can handle the precedence constraints while minimizing the net cut size. The experimental results on the MCNC benchmark circuits show that our algorithm outperforms list scheduling by a big margin, with an average improvement of over 50% for bipartitioning and 20% for multi way partitioning.

关键词： Field programmable gate arrays Reconfigurable logic Time sharing computer systems Logic devices Integrated circuit interconnections Random access memory Registers Partitioning algorithms Logic design Programmable logic arrays

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Integrating floorplanning in data-transfer based high-level synthesis

Integrating floorplanning in data-transfer based high-level ...

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ieee international conference on computer-aided Design

作者： S. Tarafdar M. Leeser Zixin Yin Synopsys Inc. Mountain View CA USA Department of Electrical and Computer Engineering Northeastern University Boston MA USA

Modern digital systems move and process vast amounts of data. Designing good ASIC architectures for these systems requires efficient data routing and storage. A high level synthesis (HLS) system must consider spatial aspects of the architecture it synthesizes to achieve this. We discuss using floorplanning information in the main HLS flow. Our HLS system, Midas, incorporates floorplanning and formulates HLS using a data transfer model. Midas synthesizes an architecture whose data storage and transfer subsystems are spatially integrated with its execution unit. Midas also generates a high level floorplan for the architecture, which contains the shapes and coordinates of its components and routing channel specifications for its buses. Our experiments comparing Midas's architectures to those generated by a HLS system that does not use the data transfer model or floorplanning show that Midas's architectures are smaller and yet allow for large amounts of simultaneous data motion and storage.

关键词： High level synthesis Design automation Integrated circuit layout Application specific integrated circuits Digital integrated circuits Integrated circuit synthesis Digital systems Routing Shape Permission

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