Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ill library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield a good...
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ISBN:
(纸本)0818682019
Traditional synthesis techniques optimize CMOS circuits in two phases i) logic minimization and ill library mapping phase. Typically, the structures and the sizes of the gates in the library are chosen to yield a good synthesis results over many blocks or even for an entire chip Consequently, this approach precludes an optimal design of individual blocks which may need custom structures. In this paper we present a new transistor level technique that optimizes CMOS circuits both structurally and size-wise. Our technique is independent of a library and hence can explore a design space much larger than that possible due to gate level optimization. Results demonstrate a significant improvement in circuit performance of our resynthesized circuits.
Formal Program running time verification is an important issue in system design required for performance optimization under ''first-time-right'' design constraints and for real-time system verification...
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ISBN:
(纸本)0818682019
Formal Program running time verification is an important issue in system design required for performance optimization under ''first-time-right'' design constraints and for real-time system verification. Simulation based approaches or simple instruction counting are not appropriate and risky for more complex architectures in particular with data dependent execution paths. Formal analysis techniques have suffered from loose timing bounds leading to significant performance penalties when strictly adhered to. We present an approach which combines simulation and formal techniques in a safe way to improve analysis precision and tighten the tinting bounds. Using a set of processor parameters, it is adaptable to arbitrary processor architectures. The results shaw an unprecedented analysis precision allowing Go reduce performance overhead for provably correct system or interface timing.
The specification language is a critical component of the hardware-software cc-design process since it is used for functional validation and as a starting point for hardware-software partitioning and Eo-synthesis. Thi...
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ISBN:
(纸本)0818682019
The specification language is a critical component of the hardware-software cc-design process since it is used for functional validation and as a starting point for hardware-software partitioning and Eo-synthesis. This paper proposes the Java programming language as a specification language for hardware-software systems. Java has ser emf characteristics that make it suitable for system specification. However, static control and dataflow analysis of Java programs is problematic because Java classes are dynamically linked. This paper provides a general solution to the problem of statically analyzing Java programs using a technique that pre-allocates most class instances and aggressively resolves memory aliasing using global analysis. The output of our analysis is a control dataflow graph for the input specification. Our results for sample designs show that the analysis can extract fine to coarse-grained concurrency far subsequent hardware-software partitioning and co-synthesis steps of the hardware-software codesign process to exploit.
We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input. After determination of the gri...
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ISBN:
(纸本)0818682019
We present a new approach to the placement problem. The proposed approach consists of analyzing the input circuit and deciding on a two-dimensional global grid for that particular input. After determination of the grid size, the placement is carried out in three steps;global placement, detailed placement, and final optimization. We will show that the output of the global placement can also serve as a fast and accurate predictor. Current implementation is based on simulated annealing. We have put all algorithms together in a placement package called NRG (pronounced N-er-G). In addition to area minimization, NRG can perform timing-driven placement. Experimental results are strong. We improve Timber Wolf's results (version 1.2, the commercial version which is suppose to be better than all university versions including version 7) by about 5 %. Our predictor can estimate the wirelength within 10-20 % accuracy offering 2-20x speedup compared with the actual placement algorithm.
Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general eno...
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Regularity extraction is an important step in the design flow of datapath-dominated circuits. This paper outlines a new method that automatically extracts regular structures from the netlist. The method is general enough to handle two types of designs: designs with structured cluster information for a portion of the datapath components that are identified at the HDL level;and designs with no such structured cluster information. The method analyzes the circuit connectivity and uses signature based approaches to recognize regularity.
The proceedings contains 107 papers from the 1997 ieeeinternationalconference on computer-aided Design. Topics discussed include: decision diagram applications;optimization and synthesis for reactive systems;estimat...
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The proceedings contains 107 papers from the 1997 ieeeinternationalconference on computer-aided Design. Topics discussed include: decision diagram applications;optimization and synthesis for reactive systems;estimation of power bounds;interconnect modeling;multi-level synthesis and covering problems;code generation and processor design;high level power prediction and reduction;noise analysis and modeling;timing analysis;microelectromechanical systems;high performance digital circuits;sequential circuit optimization;advanced scheduling techniques;clock design and optimization;circuit simulation and optimization;circuit partitioning;fault simulation and diagnosis;logic synthesis;real time systems;and interconnect optimization.
In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of minimizing the post-layout area. The propo...
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In this paper, we present an optimal algorithm for solving the simultaneous technology mapping and linear placement problem for tree-structured circuits with the objective of minimizing the post-layout area. The proposed algorithm relies on generation of gate-area versus cut-width curves using a dynamic programming approach. A novel design flow, which extends this algorithm to minimize the circuit delay and handle general DAG structures, is also presented. Experimental results on MCNC benchmarks are reported.
A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits. For ...
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A deductive technique is presented that uses voltage testing for the diagnosis of single bridging faults between two gate input or output lines and is applicable to combinational or full-scan sequential circuits. For defects in this class of faults the method is accurate by construction while making no assumptions about the logic-level wired-AND/OR behavior. A path-trace procedure starting from failing outputs deduces potential lines associated with the bridge. The information obtained from the path-trace from failing outputs is combined using an intersection graph to make further deductions. All candidate faults are implicitly represented, thereby obviating the need to enumerate faults and hence allowing the exploration of the space of all faults. Results are provided for all large ISCAS89 benchmark circuits.
With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition...
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With the remarkable growth of portable application and the increasing frequency and integration density, power is being given comparable weight to speed and area in IC designs. In technology mapping, how decomposition is done can have a significant impact on the power dissipation of the final implementation. In the literature, only heuristic algorithms are given for the low-power gate decomposition problem. In this paper, we prove many properties an optimal decomposition tree must have. Based on these optimality properties, we design an efficient exact algorithm to solve the low-power gate decomposition problem. Moreover, the exact algorithm can be easily modified to a heuristic algorithm which performs much better than the known heuristics.
Digital computer networks are playing an increasingly important role in the evaluation, distribution, integration, and management of EDA systems. Tools, libraries, design data, and a variety of both design and manufac...
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Digital computer networks are playing an increasingly important role in the evaluation, distribution, integration, and management of EDA systems. Tools, libraries, design data, and a variety of both design and manufacturing services are accessible today via networks. Networks are also playing a central role in the integration of system design teams, teams that involve a variety of both business and technical disciplines as well as widely distributed geographical locations. Throughout the history of EDA, the architectures used to integrate and distribute computation and interaction have played a central role in the overall design methodology and so have had a major, indirect impact on the choice of the most effective tools, algorithms, and data structures. In this paper, a number of the factors involved in the choice of a suitable architecture for EDA integration are reviewed and a number of ongoing developments and challenges are presented.
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