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RouteNet: Routability Prediction for Mixed -Size Designs Using Convolutional Neural Network 18

RouteNet: Routability Prediction for Mixed -Size Designs Usi...

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37th ieee/acm international conference on computer-aided Design (ICCAD)

作者： Xie, Zhiyao Huang, Yu-Hung Fang, Guan-Qi Ren, Haoxing Fang, Shao-Yun Chen, Yiran Hu, Jiang Duke Univ Durham NC 27708 USA Natl Taiwan Univ Sci & Technol Taipei Taiwan Nvidia Corp Austin TX USA Texas A&M Univ College Stn TX USA

ISBN: (纸本)9781450359504

Early routability prediction helps designers and tools perform preventive measures so that design rule violations can be avoided in a proactive manner. However, it is a huge challenge to have a predictor that is both accurate and fast. In this work, we study how to leverage convolutiortal neural network to address this challenge. The proposed method, called RouteNet, can either evaluate the overall routability of cell placement solutions without global routing or predict the locations of DRC (Design Rule Checking) hotspots. In both cases, large macros in nuxed-size designs are taken into consideration. Experiments on benchmark circuits show that RouteNet can forecast overall routability with accuracy similar to that of global router while using substantially less runtime. For DRC hotspot prediction, RouteNet improves accuracy by 50% compared to global routing. It also significantly outperforms other machine learning approaches such as support vector machine and logistic regression.

关键词： Routing computer architecture Machine learning Layout Task analysis Convolutional neural networks Runtime

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An Overview of the New acm/ieee Information Technology Curricular Framework 2

An Overview of the New ACM/IEEE Information Technology Curri...

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2nd ieee World Engineering Education conference (EDUNINE)

作者： Alrumaih, Hala Sabin, Mihaela Impagliazzo, John Al Imam Mohammad Ibn Saud Islamic Univ Riyadh Saudi Arabia Univ New Hampshire Manchester NH USA Hofstra Univ New York NY USA

ISBN: (纸本)9781538648896

acm and ieee have developed a curricular report titled, "Information Technology Curricula 2017: Curriculum Guidelines for Baccalaureate Degree Programs in Information Technology," known also as IT2017. The development of this report has received worldwide content contributions from industry and academia through surveys as well as many international conferences and workshops. An open online publication of the report was made available in December 2017. This paper presents a digest of the content of the report, the IT curricular framework, and suggestions for its use in developing new information technology programs or enhancing existing ones. The heart of the IT curricular framework is a set of competencies identified through knowledge, skills, and dispositions, as supported by pedagogical research. The paper also describes ways in which institutions could use the curricular framework not only to develop information technology degree programs, but also to improve and enhance related computing programs.

关键词： Information technology IT education IT competencies IT curricular framework IT curriculum guidelines

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Mixed size crossbar based RRAM CNN accelerator with overlapped mapping method 18

Mixed size crossbar based RRAM CNN accelerator with overlapp...

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37th ieee/acm international conference on computer-aided Design, ICCAD 2018

作者： Zhu, Zhenhua Lin, Jilan Cheng, Ming Xia, Lixue Sun, Hanbo Chen, Xiaoming Wang, Yu Yang, Huazhong Department of Electronic Engineering Tsinghua University Beijing China Beijing China State Key Laboratory of Computer Architecture Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781450359504

Convolutional Neural Networks (CNNs) play a vital role in machine learning. CNNs are typically both computing and memory intensive. Emerging resistive random-access memories (RRAMs) and RRAM crossbars have demonstrated great potentials in boosting the performance and energy efficiency of CNNs. Compared with small crossbars, large crossbars show better energy efficiency with less interface overhead. However, conventional workload mapping methods for small crossbars cannot make full use of the computation ability of large crossbars. In this paper, we propose an Overlapped Mapping Method (OMM) and MIxed Size Crossbar based RRAM CNN Accelerator (MISCA) to solve this problem. MISCA with OMM can reduce the energy consumption caused by the interface circuits, and improve the parallelism of computation by leveraging the idle RRAM cells in crossbars. The simulation results show that MISCA with OMM can achieve 2.7x speedup, 30% utilization rate improvement, and 1.2x energy efficiency improvement on average compared with fixed size crossbars based accelerator using the conventional mapping method. In comparison with GPU platform, MISCA with OMM can perform 490.4x higher on average in energy efficiency and 20x higher on average in speedup. Compared with PRIME, an existing RRAM based accelerator, MISCA has 26.4x speedup and 1.65x energy efficiency improvement. © 2018 acm.

关键词： Energy efficiency

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Security trends and advances in manufacturing systems in the era of industry 4.0 17

Security trends and advances in manufacturing systems in the...

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36th ieee/acm international conference on computer-aided Design, ICCAD 2017

作者： Chhetri, Sujit Rokka Rashid, Nafiul Faezi, Sina Faruque, Mohammad Abdullah Al Department of Electrical Engineering and Computer Science University of California IrvineCA United States

ISBN: (纸本)9781538630938

The next industrial revolution will incorporate various enabling technologies. These technologies will make the product lifecycle of the manufacturing system efficient, decentralized, and well-connected. However, these technologies have various security issues, and when integrated in the product lifecycle of manufacturing systems can pose various challenges for maintaining the security requirements such as confidentiality, integrity, and availability. In this paper, we will present the various trends and advances in the security of the product lifecycle of the manufacturing system while highlighting the roles played by the major enabling components of Industry 4.0. © 2017 ieee.

关键词： Industry 4.0

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Dynamic partitioning to mitigate stuck-at faults in emerging memories 36

Dynamic partitioning to mitigate stuck-at faults in emerging...

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36th ieee/acm international conference on computer-aided Design, ICCAD 2017

作者： Zhang, Jiangwei Kline, Donald Fang, Liang Melhem, Rami Jones, Alex K. State Key Laboratory of High Performance Computing College of Computer National University of Defense Technology China Department of Electrical and Computer Engineering University of Pittsburgh United States Department of Computer Science University of Pittsburgh United States

ISBN: (纸本)9781538630938

Emerging non-volatile memories have many advantages over conventional memory. Unfortunately, many are susceptible to write endurance challenges, resulting in stuck-at faults. Existing mitigation methods statically partition and invert data within a block containing such faults (partition-and-flip) to ensure data is written to match stuck-at cells such that they may remain in service. Unfortunately, these schemes have limited fault tolerance capabilities and require the assumption that their auxiliary bits are fault free. We propose a dynamic partitioning scheme that improves the number of tolerated stuck-at faults and simultaneously protects auxiliary bits. Dynamic partitioning can significantly improve the fault tolerance over existing static partitioning approaches with an equal number of auxiliary bits. Moreover, it can often still improve fault tolerance while reducing the number of auxiliary bits. Compared to flip-N-write and Aegis, a leading mitigation scheme, dynamic partitioning can achieve 7-72% and 5-53 x lower write error rates, respectively, for the same capacity overhead with a stuck-at-fault rate of 10-3. © 2017 ieee.

关键词： Fault tolerance

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ieee/acm international conference on computer-aided Design, digest of Technical Papers, ICCAD

IEEE/ACM International Conference on Computer-Aided Design, ...

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35th ieee/acm international conference on computer-aided Design, ICCAD 2016

ISBN: (纸本)9781450344661

The proceedings contain 133 papers. The topics discussed include: NVsim-CAM: a circuit-level simulator for emerging nonvolatile memory based content-addressable memory;design technology for fault-free and maximally-parallel wavelength-routed optical networks-on-chip;MrDP: multiple-row detailed placement of heterogeneous-sized cells for advanced nodes;security and privacy threats to on-chip non-volatile memories and countermeasures;a data locality-aware design framework for reconfigurable sparse matrix-vector multiplication kernel;a tensor-based Volterra series black-box nonlinear system identification and simulation framework;duplex: simultaneous parameter-performance exploration for optimizing analog circuits;scalable, high-quality SAT-based multi-layer escape routing;redistribution layer routing for integrated fan-out wafer-level chip-scale packages;chip editor: leveraging circuit edit for logic obfuscation and trusted fabrication;arbitrary streaming permutations with minimum memory and latency;and ICCAD-2016 CAD contest in pattern classification for integrated circuit design space analysis and benchmark suite.

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Overview of the 2017 CAD contest at ICCAD: Invited paper 36

Overview of the 2017 CAD contest at ICCAD: Invited paper

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36th ieee/acm international conference on computer-aided Design, ICCAD 2017

作者： Kim, Myung-Chul Huang, Shih-Hsu Lin, Rung-Bin Nakatake, Shigetoshi IBM Corporation AustinTX78758 United States Department of Electronic Engineering Chung Yuan Christian University Taoyuan32023 Taiwan Department of Computer Science and Engineering Yuan Ze University Taoyuan32023 Taiwan Department of Information and Media Engineering University of Kitakyushu Fukuoka808-0135 Japan

ISBN: (纸本)9781538630938

The CAD Contest at ICCAD[1], [2], [3], [4], [5], [6] is a challenging, multi-month R&D competition, focusing on modern and practical problems at the forefront of Electronic Design Automation (EDA). In its sixth year, the 2017 CAD Contest at ICCAD is among the premier worldwide academic programming contests, attracting 122 teams from 10 different regions/countries. This year, three contest problems in the areas of ECO logic synthesis, ECO routing and placement legalization for the advanced nodes are called for competition. We hope that the contest evaluation frameworks and benchmarks boost research on these critical problems and help EDA community discover novel, efficient, high-quality solutions to advance the state-of-the-art in EDA. © 2017 ieee.

关键词： Logic Synthesis

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Front-end-of-line attacks in split manufacturing 36

Front-end-of-line attacks in split manufacturing

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36th ieee/acm international conference on computer-aided Design, ICCAD 2017

作者： Wang, Yujie Cao, Tri Hu, Jiang Rajendran, Jeyavijayan College of Electronic Information and Optical Engineering Nankai University China Department of Electrical and Computer Engineering Texas AandM University United States Department of Electrical Engineering University of Texas at Dallas United States Institute of Computing Technology Chinese Academy of Sciences China

ISBN: (纸本)9781538630938

By splitting the manufacturing of integrated circuits into back-end-of-line (BEOL) and front-end-of-line (FEOL) at different foundries, the vulnerabilities to attacks by a untrusted foundry is considerably alleviated. Most previous works focus on the scenario of only BEOL attacks at untrusted FEOL foundries. In this work, we study a largely unexplored scenario, where FEOL attacks are launched by an untrusted BEOL foundry. A geometric pattern match attack and a machine learningbased attack technique are investigated. Defense techniques against the FEOL attacks are also discussed. The effectiveness of these techniques is demonstrated by experiments on benchmark circuits. © 2017 ieee.

关键词： Foundries

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Thermosiphon: A thermal aware NUCA architecture for write energy reduction of the STT-MRAM based LLCs 17

Thermosiphon: A thermal aware NUCA architecture for write en...

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36th ieee/acm international conference on computer-aided Design, ICCAD 2017

作者： Wu, Bi Cheng, Yuanqing Dai, Pengcheng Yang, Jianlei Zhang, Youguang Liu, Dijun Wang, Ying Zhao, Weisheng Fert Beijing Institute BDBC Beihang University Beijing China School of Inforamation Engineering Beihang University Beijing China School of Computer Science and Engineering Beihang University Beijing China Beijing China Institute of Computing Technology Chinese Academy of Sciences Beijing China

ISBN: (纸本)9781538630938

As the speed gap of the modern processor and the off-chip main memory enlarges, on-chip cache capacity increases to sustain the performance scaling. As a result, the cache power occupies a large portion of the total power budget. STT-MRAM (Spin Transfer Torque Magnetic Memory) is proposed as a promising solution for the low power cache design due to its high integration density and ultra-low leakage. Nevertheless, the high write power and latency of STT-MRAM become new barriers for the commercialization of this emerging technology. In this paper, we investigate the thermal effect on the access performance of STT-MRAM and observe that the temperature can affect the write delay and energy significantly. Then, we explore the NUCA (Non-Uniform Cache Access) design of the CMPs (Chip-Multi-Processors)with STT-MRAM based LLC (Last Level Cache). A thermal aware data migration policy, called 'Thermosiphon', which takes advantage of the thermal property of STT-MRAM, is proposed to reduce the LLC write energy. This policy splits the LLC into different regions based on the thermal distribution and adaptively migrate write intensive data considering the temperature gradient among different thermal regions. Compared to the conventional NUCA design, our proposed design can save 22.5% write energy with negligible hardware overhead. © 2017 ieee.

关键词： Budget control

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Introducing a Reliability Analysis Framework for High Performance Computing Environments

Introducing a Reliability Analysis Framework for High Perfor...

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international conference on Advances in Social Network Analysis and Mining, ASONAM

作者： S. Sharma A. D. Clark Whiting School of Engineering Johns Hopkins University Baltimore Maryland Lane Department of Computer Science and Electrical Engineering West Virginia University Morgantown West Virginia

ISBN: (纸本)9781538660522

Supercomputing environments are becoming the norm for daily use. However, their complex infrastructure makes troubleshooting and monitoring failures extremely difficult. This is because these infrastructures contain thousands of nodes representing various applications and processors. To address these concerns, we propose a real-time reliability analysis framework for high performance computing (HPC) environments where the contributions are three-fold. First, an improved data network extrapolation (DNE) methodology is proposed as a pre-processing module. This component incorporates the system failure information (i.e. job, fault, and error log files) and performs robust job-based failure accounting for sequential and parallel jobs. This element also performs cross-referencing to compute task-based failure accounting, where the assumption is made that tasks are comprised of either one or more jobs. Next, a reliability characterization and analysis (RCA) schema is proposed that takes the failure information from the DNE process to perform survival analyses on each individual node in addition to the entire reliability infrastructure. This is coupled with a failure metrics characterization (FMC) schema that estimates the failure metrics such as the mean time to failure (MTTF) as well as the hazard rate. Additionally, a comparative analysis is made between the Log-Normal or Weibull distributions in terms of modeling job and task-based failure activity. Empirical analysis using the Structural Simulation Toolkit (SST) illustrate the promise of this approach in terms of characterizing, monitoring, and troubleshooting failure behavior. The results of this work can aide systems administrators the dynamic tools to pinpoint and monitor failure behavior; its impacts; and alternative job-scheduling policies without interrupting production processes.

关键词： Reliability Task analysis Monitoring Measurement Extrapolation Hazards High performance computing

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