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检索条件"任意字段=IEEE/ACM International Conference on Computer Aided Design"

共 22426 条记录，以下是101-110 订阅

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RankTuner: When design Tool Parameter Tuning Meets Preference Bayesian Optimization 24

RankTuner: When Design Tool Parameter Tuning Meets Preferenc...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Xu, Peng Zheng, Su Ye, Yuyang Bai, Chen Xu, Siyuan Geng, Hao Ho, Tsung-Yi Yu, Bei The Chinese University of Hong Kong Hong Kong Huawei Noah’s Ark Lab Canada ShanghaiTech University China

ISBN: (纸本)9798400710773

Electronic design Automation (EDA) tools are critical in the Very Large Scale Integration (VLSI) flow. To address the challenges posed by the extensive search space and intricate feature interactions, statistical and machine-learning methods have been employed. These methods aim to model tool parameters and treat the tuning process as a regression task. However, these regression-based methods suffer from inaccurate estimations owing to limited training samples. To address this issue, we propose a ranking-based tool parameter tuning framework, called RankTuner, which directly learns the dominant relationship between parameters. RankTuner utilizes a pairwise Gaussian process to estimate the probability and uncertainty of the dominance relationship. Our approach also integrates a Duel-Thompson sampling method to balance exploration and exploitation in parameter selections. A dimensionality reduction scheme with random embedding and trust region techniques is incorporated to enable parallel searches. Experimental results demonstrate the superiority of RankTuner compared to the cutting-edge tool parameter tuning methods. © 2024 Copyright is held by the owner/author(s).

关键词： Dimensionality reduction

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AdapMoE: Adaptive Sensitivity-based Expert Gating and Management for Efficient MoE Inference 24

AdapMoE: Adaptive Sensitivity-based Expert Gating and Manage...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Zhong, Shuzhang Liang, Ling Wang, Yuan Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China

ISBN: (纸本)9798400710773

Mixture-of-Experts (MoE) models are designed to enhance the efficiency of large language models (LLMs) without proportionally increasing the computational demands. However, their deployment on edge devices still faces significant challenges due to high on-demand loading overheads from managing sparsely activated experts. This paper introduces AdapMoE, an algorithm-system co-design framework for efficient MoE inference. AdapMoE features adaptive expert gating and management to reduce the on-demand loading overheads. We observe the heterogeneity of experts loading across layers and tokens, based on which we propose a sensitivity-based strategy to adjust the number of activated experts dynamically. Meanwhile, we also integrate advanced prefetching and cache management techniques to further reduce the loading latency. Through comprehensive evaluations on various platforms, we demonstrate AdapMoE consistently outperforms existing techniques, reducing the average number of activated experts by 25% and achieving a 1.35× speedup without accuracy degradation. Code is available at: https://***/PKU-SEC-Lab/AdapMoE. © 2024 Copyright is held by the owner/author(s).

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OpenLLM-RTL: Open Dataset and Benchmark for LLM-aided design RTL Generation 24

OpenLLM-RTL: Open Dataset and Benchmark for LLM-Aided Design...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Liu, Shang Lu, Yao Fang, Wenji Li, Mengming Xie, Zhiyao Hong Kong

ISBN: (纸本)9798400710773

The automated generation of design RTL based on large language model (LLM) and natural language instructions has demonstrated great potential in agile circuit design. However, the lack of datasets and benchmarks in the public domain prevents the development and fair evaluation of LLM solutions. This paper highlights our latest advances in open datasets and benchmarks from three perspectives: (1) RTLLM 2.0, an updated benchmark assessing LLM’s capability in design RTL generation. The benchmark is augmented to 50 hand-crafted designs. Each design provides the design description, test cases, and a correct RTL code. (2) AssertEval, an open-source benchmark assessing the LLM’s assertion generation capabilities for RTL verification. The benchmark includes 18 designs, each providing specification, signal definition, and correct RTL code. (3) RTLCoder-Data, an extended open-source dataset with 80K instruction-code data samples. Moreover, we propose a new verification-based method to verify the functionality correctness of training data samples. Based on this technique, we further release a dataset with 7K verified high-quality samples. These three studies are integrated into one framework, providing off-the-shelf support for the development and evaluation of LLMs for RTL code generation and verification. Finally, extensive experiments indicate that LLM performance can be boosted by enlarging the training dataset, improving data quality, and improving the training scheme. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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ADO-LLM: Analog design Bayesian Optimization with In-Context Learning of Large Language Models 24

ADO-LLM: Analog Design Bayesian Optimization with In-Context...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Yin, Yuxuan Wang, Yu Xu, Boxun Li, Peng Department of Electronic and Computer Engineering University of California Santa BarbaraCA United States

ISBN: (纸本)9798400710773

Analog circuit design requires substantial human expertise and involvement, which is a significant roadblock to design productivity. Bayesian Optimization (BO), a popular machine-learning-based optimization strategy, has been leveraged to automate analog design given its applicability across various circuit topologies and technologies. Traditional BO methods employ black-box Gaussian Process surrogate models and optimized labeled data queries to find optimization solutions by trading off between exploration and exploitation. However, the search for the optimal design solution in BO can be expensive from both a computational and data usage point of view, particularly for high-dimensional optimization problems. This paper presents ADO-LLM, the first work integrating large language models (LLMs) with Bayesian Optimization for analog design optimization. ADO-LLM leverages the LLM’s ability to infuse domain knowledge to rapidly generate viable design points to remedy BO’s inefficiency in finding high-value design areas specifically under the limited design space coverage of the BO’s probabilistic surrogate model. In the meantime, sampling of design points evaluated in the iterative BO process provides quality demonstrations for the LLM to generate high-quality design points while leveraging infused broad design knowledge. Furthermore, the diversity brought by BO’s exploration enriches the contextual understanding of the LLM and allows it to more broadly search in the design space and prevent repetitive and redundant suggestions. We evaluate the proposed framework on two different types of analog circuits and demonstrate notable improvements in design efficiency and effectiveness. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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FloorSet - a VLSI Floorplanning Dataset with design Constraints of Real-World SoCs 24

FloorSet - a VLSI Floorplanning Dataset with Design Constrai...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Mallappa, Uday Mostafa, Hesham Galkin, Mikhail Phielipp, Mariano Majumdar, Somdeb Intel Labs United States

ISBN: (纸本)9798400710773

Floorplanning for systems-on-a-chip (SoCs) and its sub-systems is a crucial and non-trivial step of the physical design flow. It represents a difficult combinatorial optimization problem. A typical large scale SoC with 120 partitions generates a search-space of ~ 10250. As novel machine learning (ML) approaches emerge to tackle such problems, there is a growing need for a modern benchmark that comprises a large training dataset and performance metrics that better reflect real-world constraints and objectives compared to existing benchmarks. To address this need, we present FloorSet - two comprehensive datasets of synthetic fixed-outline floorplan layouts that reflect the distribution of real SoCs. Each dataset has 1M training samples and 100 test samples where each sample is a synthetic floorplan. FloorSet-Prime comprises fully-abutted rectilinear partitions and near-optimal wire-length. A simplified dataset that reflects early design phases, FloorSet-Lite comprises rectangular partitions, with 1 © 2024 Copyright is held by the owner/author(s).

关键词： Constrained optimization

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Partial Differential Equation Acceleration by Exploiting Value Similarity 24

Partial Differential Equation Acceleration by Exploiting Val...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Li, Zehua Ma, Kaisheng Xi’an Jiaotong University Shaanxi Xi An China Shaanxi Xi An China Tsinghua University Beijing China

ISBN: (纸本)9798400710773

Partial Differential Equations (PDEs) are integral in modeling various scientific and engineering phenomena. One of the most common numerical solutions for these equations is the Finite Difference Method (FDM), which reformulates derivatives into stencil computation patterns. FDM’s reliance on various discretized mesh points and high-precision numerical iterations necessitates substantial memory storage and floating-point computations. This paper presents VSAP, an efficient algorithm-hardware co-design incorporating temporal and spatial similarity considerations. Initially, we propose a hybrid data compression scheme that exploits value similarity in one timestep. We implemented this compression algorithm using specialized hardware. Secondly, capitalizing on the characteristic of slow value changes during iterations, we design a bit-slice computation approach. It only retains and processes the effective slices that substantially impact the outcome. Thirdly, we design a computation module that prioritizes summation operation before multiplication. It further reduces the overhead of computation units in conjunction with bit-slice mode. In cases employing both spatial and temporal tiling, VSAP attains an average speedup of 23.2×, 7.9×, 3.2× over Intel Xeon CPU, NVIDIA A100 GPU, and FDMAX accelerator across four well-known PDE problems. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine 24

Multi-Phase Coupled CMOS Ring Oscillator based Potts Machine

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Gonul, Yilmaz Ege Taskin, Baris Department of Electrical and Computer Engineering Drexel University PhiladelphiaPA United States

ISBN: (纸本)9798400710773

This paper presents a coupled ring oscillator based Potts machine to solve NP-hard combinatorial optimization problems (COPs). Potts model is a generalization of the Ising model, capturing multivalued spins in contrast to the binary-valued spins allowed in the Ising model. Similar to recent literature on Ising machines, the proposed architecture of Potts machines implements the Potts model with interacting spins represented by coupled ring oscillators. Unlike Ising machines which are limited to two spin values, Potts machines model COPs that require a larger number of spin values. A major novelty of the proposed Potts machine is the utilization of the N-SHIL (Sub-Harmonic Injection Locking) mechanism, where multiple stable phases are obtained from a single (i.e. ring) oscillator. In evaluation, 3-coloring problems from the DIMACS SATBLIB benchmark and two randomly generated larger problems are mapped to the proposed architecture. The proposed architecture is demonstrated to solve problems of varying size with 89% to 92% accuracy averaged over multiple iterations. The simulation results show that there is no degradation in accuracy, no significant increase in solution time, and only a linear increase in power dissipation with increasing problem sizes up to 2000 nodes. © 2024 Copyright is held by the owner/author(s).

关键词： Ising model

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Hardware-Aware Quantization for Accurate Memristor-Based Neural Networks 24

Hardware-Aware Quantization for Accurate Memristor-Based Neu...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Diware, Sumit Yaldagard, Mohammad Amin Bishnoi, Rajendra Computer Engineering Lab Delft University of Technology Delft Netherlands

ISBN: (纸本)9798400710773

Memristor-based Computation-In-Memory (CIM) has emerged as a compelling paradigm for designing energy-efficient neural network hardware. However, memristors suffer from conductance variation issue, which introduces computational errors in CIM hardware and leads to a degraded inference accuracy. In this paper, we present a hardware-aware quantization to mitigate the impact of conductance variation on CIM-based neural networks. We achieve this using the inherent characteristics of fixed-point arithmetic in CIM hardware. By tuning the bit-precision of weights, we align the conductance variation-induced errors with lower-order output bits. This reduces their numerical impact on the fixed-point output. We further decrease the residual errors by selectively discarding bits with low information and high error. This leads to error-free computations and a high inference accuracy. Our proposed methodology achieves 5.6× correct operations per unit energy compared to the conventional approach, while incurring very low hardware overheads. © 2024 Copyright is held by the owner/author(s).

关键词： Fixed point arithmetic

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Physically Aware Synthesis Revisited: Guiding Technology Mapping with Primitive Logic Gate Placement 24

Physically Aware Synthesis Revisited: Guiding Technology Map...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Pan, Hongyang Lan, Cunqing Liu, Yiting Wang, Zhiang Shang, Li Zeng, Xuan Yang, Fan Zhu, Keren State Key Lab of Integrated Circuits and Systems School of Microelectronics Fudan University China School of Computer Science Fudan University China Department of Electrical and Computer Engineering University of California San Diego United States

ISBN: (纸本)9798400710773

A typical VLSI design flow is divided into separated front-end logic synthesis and back-end physical design (PD) stages, which often require costly iterations between these stages to achieve design closure. Existing approaches face significant challenges, notably in utilizing feedback from physical metrics to better adapt and refine synthesis operations, and in establishing a unified and comprehensive metric. This paper introduces a new Primitive logic gate placement guided technology MAPping (PigMAP) framework to address these challenges. With approximating technology-independent spatial information, we develop a novel wirelength (WL) driven mapping algorithm to produce PD-friendly netlists. PigMAP is equipped with two schemes: a performance mode that focuses on optimizing the critical path WL to achieve high performance, and a power mode that aims to minimize the total WL, resulting in balanced power and performance outcomes. We evaluate our framework using the EPFL benchmark suites with ASAP7 technology, using the OpenROAD tool for place-and-route. Compared with OpenROAD flow scripts, performance mode reduces delay by 14% while increasing power consumption by only 6%. Meanwhile, power mode achieves a 3% improvement in delay and a 9% reduction in power consumption. © 2024 Copyright is held by the owner/author(s).

关键词： Logic design

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Is Vanilla Bayesian Optimization Enough for High-Dimensional Architecture design Optimization? 24

Is Vanilla Bayesian Optimization Enough for High-Dimensional...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Gao, Yuanhang Luo, Donger Bai, Chen Yu, Bei Geng, Hao Sun, Qi Zhuo, Cheng Zhejiang University China ShanghaiTech University China Chinese University of Hong Kong Hong Kong State Key Laboratory of Integrated Chips and Systems China

ISBN: (纸本)9798400710773

In the tide of explosive development in artificial intelligence (AI), the design of AI System-on-Chips (SoCs) is an urgently pressing issue that needs to be addressed. The application of design Space Exploration (DSE) methods is paramount in pursuing a sound microarchitecture design and improving the quality of results. However, the high-dimensional design parameters and huge design space, which normally occur in the complicated SoCs for Large Language Model (LLM) tasks, pose a great challenge to existing techniques. In this paper, a novel and explainable Bayesian optimization-based framework MCT-Explorer is proposed. A Monte Carlo Tree Search (MCTS)-based method is utilized to analyze the importance of design parameters, guide the sampling directions, mitigate low-quality performance modeling issues, and further improve optimization efficiency. Besides, an information-guided multi-objective optimization function is adopted to balance the multiple metrics (e.g., Cycle. Area, and Power) for SoC design. Our approach can provide guiding opinions and deeper insights for parameter optimization, thus transcending previous arts and achieving an explainable model. Experiment results demonstrate the extraordinary performance of our framework in various high-dimensional (up to hundreds of parameters) and complicated LLM SoC designs. © 2024 Copyright is held by the owner/author(s).

关键词： Intellectual property core

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