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检索条件"任意字段=IEEE/ACM International Conference on Computer Aided Design"

共 22426 条记录，以下是131-140 订阅

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FlexHE: a Flexible Kernel Generation Framework for Homomorphic Encryption-Based Private Inference 24

FlexHE: a Flexible Kernel Generation Framework for Homomorph...

引用

43rd international conference on computer-aided design, ICCAD 2024

作者： Yu, Jiangrui Zeng, Wenxuan Xu, Tianshi Chen, Renze Liang, Yun Wang, Runsheng Huang, Ru Li, Meng Institute for Artificial Intelligence Peking University Beijing China School of Integrated Circuits Peking University Beijing China Institute of Electronic Design Automation Peking University Wuxi China Beijing Advanced Innovation Center for Integrated Circuits Beijing China School of Software and Microelectronics Peking University Beijing China School of Computer Science Peking University Beijing China

ISBN: (纸本)9798400710773

Secure two-party computation (2PC) based on homomorphic encryption (HE) achieves formal data privacy protection and gets increasing adoption for private deep neural network (DNN) inference. As modern HE schemes usually operate on polynomials, existing works rely on manually-designed HE kernels for representative DNN operations. However, this is not only unscalable considering the diverse operator types, shapes, polynomial orders, etc, but also misses important optimization opportunities. In this paper, we introduce FlexHE, a flexible kernel generation framework to enable automatic generation and optimization of HE kernels for 2PC-based private inference. Given a high-level description of DNN operations, FlexHE can systematically define the HE kernel design space considering various optimization dimensions, including loop tiling, reordering, etc. We also analyze the communication and computation impact of different optimization dimensions for design space reduction. To search for the best kernel design, a two-level optimization problem is formulated and iteratively solved with an integer linear programming (ILP) formulation. With extensive experimental results, we not only demonstrate a better coverage of DNN operations including depth-wise Conv3D and dilated Conv3D, but also achieve more than 100×, 7.9×, and 4.2× latency reduction compared to prior-art HElayers, Cheetah, and Falcon, respectively. © 2024 Copyright is held by the owner/author(s).

关键词： Linear programming

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Co-designing Binarized Transformer and Hardware Accelerator for Efficient End-to-End Edge Deployment 24

Co-Designing Binarized Transformer and Hardware Accelerator ...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Ji, Yuhao Fang, Chao Ma, Shaobo Shao, Haikuo Wang, Zhongfeng School of Electronic Science and Engineering Nanjing University Nanjing China Department of Computer Science and Engineering Chinese University of Hong Kong Hong Kong School of Integrated Circuits Sun Yat-sen University Shenzhen China

ISBN: (纸本)9798400710773

Transformer models have revolutionized AI tasks, but their large size hinders real-world deployment on resource-constrained and latency-critical edge devices. While binarized Transformers offer a promising solution by significantly reducing model size, existing approaches suffer from algorithm-hardware mismatches with limited co-design exploration, leading to suboptimal performance on edge devices. Hence, we propose a co-design method for efficient end-to-end edge deployment of Transformers from three aspects: algorithm, hardware, and joint optimization. First, we propose BMT, a novel hardware-friendly binarized Transformer with optimized quantization methods and components, and we further enhance its model accuracy by leveraging the weighted ternary weight splitting training technique. Second, we develop a streaming processor mixed binarized Transformer accelerator, namely BAT, which is equipped with specialized units and scheduling pipelines for efficient inference of binarized Transformers. Finally, we co-optimize the algorithm and hardware through a design space exploration approach to achieve a global trade-off between accuracy, latency, and robustness for real-world deployments. Experimental results show our co-design achieves up to 2.14~49.37× throughput gains and 3.72~88.53× better energy efficiency over state-of-the-art Transformer accelerators, enabling efficient end-to-end edge deployment. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit layout

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Accurate, Yet Scalable: A SPICE-based design and Optimization Framework for eNVM-based Analog In-memory Computing 24

Accurate, Yet Scalable: A SPICE-based Design and Optimizatio...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Mojahidul Ahsan, S.M. Shahriar, Muhammad Sakib Chowdhury, Mrittika Hossain, Tanvir Hasan, Md Sakib Hoque, Tamzidul Department of Electrical Engineering and Computer Science University of Kansas LawrenceKS United States Department of Electrical and Computer Engineering University of Mississippi OxfordMS United States

ISBN: (纸本)9798400710773

This paper introduces a scalable SPICE-based tool infrastructure designed to optimize analog compute-in-memory (ACIM) architectures utilizing emerging non-volatile resistive memory (eNVM) technologies. The inherent efficiency of analog eNVM crossbar arrays in performing matrix-vector multiplications significantly enhances the power, performance, and area efficiency of edge AI devices and other applications. Our framework addresses the challenges of accurately simulating ACIM architectures, which are highly susceptible to variations in process, voltage, temperature, and analog noise. The framework uses SPICE for accurate analog and mixed-signal circuit simulation. It automates the generation of SPICE-level ACIM designs for deep neural networks. Additionally, it speeds up the simulation runtime by up to 35× for large DNN models while maintaining the same SPICE-level accuracy. Moreover, it ensures simulation convergence for large netlists, facilitating SPICE simulation of large-scale eNVM crossbars that were previously impractical. We demonstrated that our framework is capable of simulating inference using netlists for MLPs with over 800,000 parameters trained on the MNIST dataset within acceptable runtime, where contemporary SPICE simulators do not even converge. We validated the simulation results in terms of inference accuracy, which shows less than a 3.8% accuracy drop compared to software-based inference results. Lastly, we demonstrated the integration of our framework with an architectural simulator, facilitating comprehensive system-level simulation. © 2024 Copyright is held by the owner/author(s).

关键词： Deep neural networks

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ConSmax: Hardware-Friendly Alternative Softmax with Learnable Parameters 24

ConSmax: Hardware-Friendly Alternative Softmax with Learnabl...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Liu, Shiwei Tao, Guanchen Zou, Yifei Chow, Derek Fan, Zichen Lei, Kauna Pan, Bangfei Sylvester, Dennis Kielian, Gregory Saligane, Mehdi Google Research United States Department of Electrical Engineering and Computer Sciences University of Michigan United States

ISBN: (纸本)9798400710773

The self-attention mechanism distinguishes transformer-based large language models (LLMs) apart from convolutional and recurrent neural networks. Despite the performance improvement, achieving real-time LLM inference on silicon remains challenging due to the extensive use of Softmax in self-attention. In addition to the non-linearity, the low arithmetic intensity significantly limits processing parallelism, especially when working with longer contexts. To address this challenge, we propose Constant Softmax (ConSmax), a software-hardware co-design that serves as an efficient alternative to Softmax. ConSmax utilizes differentiable normalization parameters to eliminate the need for maximum searching and denominator summation in Softmax. This approach enables extensive parallelization while still executing the essential functions of Softmax. Moreover, a scalable ConSmax hardware design with a bitwidth-split look-up table (LUT) can achieve lossless non-linear operations and support mixed-precision computing. Experimental results show that ConSmax achieves a minuscule power consumption of 0.2mW and an area of 0.0008mm2 at 1250MHz working frequency in 16nm FinFET technology. For open-source contribution, we further implement our design with the OpenROAD toolchain under SkyWater’s 130nm CMOS technology. The corresponding power is 2.69mW and the area is 0.007mm2. ConSmax achieves 3.35× power savings and 2.75× area savings in 16nm technology, and 3.15× power savings and 4.14× area savings with the open-source EDA toolchain. In the meantime, it also maintains comparable accuracy on the GPT-2 model and the WikiText103 dataset. The project is available at https://***/ReaLLMASIC/ConSmax. © 2024 Copyright is held by the owner/author(s).

关键词： Table lookup

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BPINN-EM: Fast Stochastic Analysis of Electromigration Damage using Bayesian Physics-Informed Neural Networks 24

BPINN-EM: Fast Stochastic Analysis of Electromigration Damag...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Lamichhane, Subed Kavousi, Mohamadamir Tan, Sheldon X.-D. Department of Electrical and Computer Engineering University of California RiversideCA92521 United States

ISBN: (纸本)9798400710773

Electromigration (EM) induced aging and degradation in interconnect wires is inherently a stochastic process, with lifetime typically measured in terms of mean time to failure at both wire and circuit levels. However, existing approaches still incur high computing costs, as computing both means and variances is generally expensive. In this work, we propose a novel fast variational analysis framework to tackle the challenges of stochastic estimation of EM stress evolution in multi-segment interconnect wires. We utilize Bayesian networks in conjunction with the recently introduced hierarchical (two-step) physics-informed neural networks (PINN). The resulting method, termed BPINN-EM, enables rapid variational stress analysis of metal wires by leveraging the robust uncertainty quantification capability of Bayesian networks with expedited training over small dataset. Moreover, we devise BPINN-EM to incorporate Bayesian networks only in the first stage of the hierarchical PINN, thereby circumventing the need for sampling across the entire PINN level during training and significantly reducing training costs. Our results on several general multi-segment interconnect structure demonstrate that the proposed BPINN-EM approach is much more efficient than conventional baselines and state-of-the-art algorithms. Compared to a Monte Carlo simulator implemented in COMSOL, BPINN-EM offers a 240× speedup. Moreover, compared to the recently proposed EMSpice simulated by the Monte Carlo method, the new method provides more than an 85× speedup with almost no loss of accuracy. © 2024 Copyright is held by the owner/author(s).

关键词： Monte Carlo methods

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MEIC: Re-thinking RTL Debug Automation using LLMs 24

MEIC: Re-thinking RTL Debug Automation using LLMs

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43rd international conference on computer-aided design, ICCAD 2024

作者： Xu, Ke Sun, Jialin Hu, Yuchen Fang, Xinwei Shan, Weiwei Wang, Xi Jiang, Zhe National Center of Technology Innovation for EDA School of Integrated Circuits Southeast University China Department of Computer Science University of York United Kingdom

ISBN: (纸本)9798400710773

The deployment of Large Language Models (LLMs) for code debugging (e.g., C and Python) is widespread, benefiting from their ability to understand and interpret intricate concepts. However, in the semiconductor industry, utilising LLMs to debug Register Transfer Level (RTL) code is still insufficient, largely due to the underrepresentation of RTL-specific data in training sets. This work introduces a novel framework, Make Each Iteration Count (MEIC), which contrasts with traditional one-shot LLM-based debugging methods that heavily rely on prompt engineering, model tuning, and model training. MEIC utilises LLMs in an iterative process to overcome the limitation of LLMs in RTL code debugging, which is suitable for identifying and correcting both syntax and function errors, while effectively managing the uncertainties inherent in LLM operations. To evaluate our framework, we provide an open-source dataset comprising 178 common RTL programming errors. The experimental results demonstrate that the proposed debugging framework achieves fix rate of 93% for syntax errors and 78% for function errors, with up to 48x speedup in debugging processes when compared with experienced engineers. The Repo. of dataset and code: https://***/SEU-ACAL/reproduce-MEIC-ICCAD. © 2024 Copyright is held by the owner/author(s).

关键词： Program debugging

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FSMM: An Efficient Matrix Multiplication Accelerator Supporting Flexible Sparsity 24

FSMM: An Efficient Matrix Multiplication Accelerator Support...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Qiao, Yuxuan Yang, Fan Zhang, Yecheng Xiong, Xiankui Yao, Xiao Yao, Haidong State Key Laboratory of Integrated Chips and Systems Fudan University Shanghai China School of Microelectronics Fudan University Shanghai China State Key Laboratory of Mobile Network and Mobile Multimedia Technology ZTE Corporation Shenzhen China

ISBN: (纸本)9798400710773

Sparse matrix multiplication is a critical operation in deep learning. However, matrix sparsity leads to irregular data flow, which would degrade the efficiency of matrix multiplication. Traditional accelerators, equipped with additional hardware units to address this issue, often experience the issue of low hardware utilization. Furthermore, N : M structured sparsity and corresponding hardware architectures face challenges such as accuracy degradation, limited flexibility, and restricted applicability. In this paper, we propose a Flexible Sparse Matrix Multiplication Accelerator (FSMM), which can improve the efficiency of sparse matrix multiplication through both algorithmic-level and hardware-level optimizations. At the algorithmic level, we propose the matrix-matrix multiplication with block-level outer production and fine-grained matrix reordering algorithm. The algorithm balances the sparsity of each column of a matrix block, which improves matrix compression, balances the load, and speeds up computation. This algorithm reduces storage by 8.2% ~ 85.9%. At the hardware-level, we introduce a flexible architecture for matrix multiplication. It selects the most suitable data path to complete matrix multiplication based on the sparsity of the reordered matrix. FSMM achieves a speedup of 1.90× ~ 16.18× over Systolic Array and 1.70× ~ 2.87× over the existing TSTC approach. © 2024 Copyright is held by the owner/author(s).

关键词： Fast response computer systems

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HLSPilot: LLM-based High-Level Synthesis 24

HLSPilot: LLM-based High-Level Synthesis

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43rd international conference on computer-aided design, ICCAD 2024

作者： Xiong, Chenwei Liu, Cheng Li, Huawei Li, Xiaowei SKLP Institute of Computing Technology Chinese Academy of Sciences Beijing China Dept. of Computer Science University of Chinese Academy of Sciences Beijing China

ISBN: (纸本)9798400710773

Large language models (LLMs) have catalyzed an upsurge in automatic code generation, garnering significant attention for register transfer level (RTL) code generation. Despite the potential of RTL code generation with natural language, it remains error-prone and limited to relatively small modules because of the substantial semantic gap between natural language expressions and hardware design intent. In response to the limitations, we propose a methodology that reduces the semantic gaps by utilizing C/C++ for generating hardware designs via High-Level Synthesis (HLS) tools. Basically, we build a set of C-to-HLS optimization strategies catering to various code patterns, such as nested loops and local arrays. Then, we apply these strategies to sequential C/C++ code through in-context learning, which provides the LLMs with exemplary C/C++ to HLS prompts. With this approach, HLS designs can be generated effectively. Since LLMs still face problems in determining the optimized pragma parameters precisely, we have a design space exploration (DSE) tool integrated for pragma parameter tuning. Furthermore, we also employ profiling tools to pinpoint the performance bottlenecks within a program and selectively convert bottleneck components to HLS code for hardware acceleration. By combining the LLM-based profiling, C/C++ to HLS translation, and DSE, we have established HLSPilot—the first LLM-enabled high-level synthesis framework, which can fully automate the high-level application acceleration on hybrid CPU-FPGA architectures. According to our experiments on real-world application benchmarks, HLSPilot achieve comparable performance in general and can even outperform manually crafted counterparts, thereby underscoring the substantial promise of LLM-assisted hardware designs. © 2024 Copyright is held by the owner/author(s).

关键词： High level synthesis

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Modern Fixed-Outline Floorplanning with Rectilinear Soft Modules 24

Modern Fixed-Outline Floorplanning with Rectilinear Soft Mod...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Chen, Yu-Yang Lin, Yi-Chen Hsu, Tzu-Han Jiang, Iris Hui-Ru Chen, Tung-Chieh Chen, Tai-Chen Chang, Hua-Yu Graduate Institute of Electronics Engineering National Taiwan University Taipei Taiwan Design Technology Group Synopsys Inc. Taipei Taiwan

ISBN: (纸本)9798400710773

To better utilize space and reduce wirelength within a fixed-outline with preplaced modules, modern floorplanning is desired to be able to handle rectilinear soft modules. Nevertheless, the induced special shape constraints have not been fully explored in the literature. In this paper, we propose a novel analytical-based approach to address the challenges of fixed-outline, preplaced modules, and rectilinear soft modules. Unlike most previous work, which abstracts modules as circles during global floorplanning, we treat modules as shape-adjustable rectangles and propose a differentiable shape mechanism to capture the impact of shaping on the floorplan quality. For legalization, we first construct an overlap graph to extract the neighborhood of overlaps, modules, and whitespaces. Then, a shortest-path based algorithm effectively migrates area from overlaps through a chain of modules to whitespaces while carefully considering the shape constraints. Finally, we iteratively expand and shrink the bounding boxes of modules to further refine the wirelength by improving area utilization. Our legalization and refinement allows rectilinear shapes to form naturally. Based on the experiments conducted on the GSRC, MCNC, and CAD contest benchmark suites, our results show that our approach achieves superior wirelength and runtime to the state-of-the-art works and the contest winning team, demonstrating its effectiveness and efficiency. © 2024 Copyright is held by the owner/author(s).

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FAS-Trans: Fully Exploiting FFN and Attention Sparsity for Transformer on FPGA 24

FAS-Trans: Fully Exploiting FFN and Attention Sparsity for T...

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43rd international conference on computer-aided design, ICCAD 2024

作者： Wang, Hongji Zhang, Yifan Yu, Jun Wang, Kun School of Microelectronics Fudan University Shanghai China

ISBN: (纸本)9798400710773

Transformers have increasingly become the backbone of modern AI, excelling in tasks across natural language processing (NLP) and computer vision (CV). However, deploying them on resource-constrained platforms is challenging due to their high computational and energy demands. Previous efforts primarily focused on reducing the computational load of the self-attention module in Transformers, often neglecting optimization for other parts, like feed-forward network (FFN) modules. To address this gap, we propose FAS-Trans, an innovative algorithm-architecture co-design accelerator that efficiently optimizes both self-attention and FFN modules. FAS-Trans incorporates an innovative approximate prediction mechanism utilizing shifted-adders, which pre-estimates matrix sparsity to further reduce computational loads. This mechanism also enables reusing approximate prediction values in subsequent exact computations. Moreover, our approach includes cross-stage sparsity prediction for self-attention module to minimize computations involved in both QKV generation and attention computing. In the FFN module, we predict and exploit sparsity of FC1 block and employ low-precision multipliers for values close to zero, significantly cutting down FFN computational overhead. Our dedicated hardware architecture can effectively handle the irregularities of sparsity and multi-precision, ensuring high hardware resource utilization. Comprehensive evaluations across multiple benchmarks demonstrate that FAS-Trans reduces normalized computational overhead by 41.9% on average with 1% loss in accuracy. FAS-Trans can achieve 2.39-27.98× speedup and 18.9-72.6× energy efficiency improvement compared with CPU and GPU acceleration. Furthermore, we observe that FAS-Trans achieves 2.15-3.80× speedup, 1.87-19.89× improvement in throughput and 2.4-5.6× improvement in energy efficiency compared with other FPGA-based Transformer accelerators. © 2024 Copyright is held by the owner/author(s).

关键词： Integrated circuit design

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