The proceedings contain 135 papers from the ICCAD - 2004 - ieee/acminternationalconference on computer-aideddesign, Digest of Technical Papers. The topics discussed include: statistical design and optimization of S...
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The proceedings contain 135 papers from the ICCAD - 2004 - ieee/acminternationalconference on computer-aideddesign, Digest of Technical Papers. The topics discussed include: statistical design and optimization of SRAM cell for yield enhancement;DAG-aware circuit compression for formal verification;dynamic transition relation simplification for bounded property checking;fast simulation of VLSI interconnects;a soft error rate analysis (SERA) methodology;the care and feeding of your statistical static timer;a robust cell-level crosstalk delay change analysis;delay noise pessimism reduction by logic correlations;debugging sequential circuits using Boolean satisfiability;and towards formal verification of analog designs.
The proceedings contains 109 papers from the 1998 ieeeinternationalconference on computer-aideddesign. Topics discussed include: circuit simulation;layout and logic synthesis;dynamic system synthesis;design for tes...
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The proceedings contains 109 papers from the 1998 ieeeinternationalconference on computer-aideddesign. Topics discussed include: circuit simulation;layout and logic synthesis;dynamic system synthesis;design for testability;reduced order modeling;combinatorial logic synthesis;sequential circuit testing;numerical techniques for simulation and extraction;intellectual property protection;estimating noise in radio frequency systems;noise in digital systems;pass transistor and domino logic synthesis;floorplanning;test generation techniques;analog circuit synthesis;timing optimization in sequential synthesis;high-level synthesis;sequential verificational;memory and interfaces synthesis;and power estimation.
The proceedings contains 101 papers from the 1996 internationalconference on computeraideddesign. Topics discussed include: technology mapping;interconnect characterization and analysis;high performance routing syn...
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The proceedings contains 101 papers from the 1996 internationalconference on computeraideddesign. Topics discussed include: technology mapping;interconnect characterization and analysis;high performance routing synthesis;sequential circuit testing;formal verification;system design synthesis and compilation;timing analysis;high level design;power and performance in high level synthesis;high performance circuit optimization;circuit partitioning;automatic test pattern generation (ATPG);embedded applications;implication-based logic synthesis;advance numerical simulation techniques;robust routing;yield and technology modeling;power and timing analysis;verification and fault tolerance;and analog CAD and methodology.
The conference materials contain 109 papers. design for testability, technology driven IC layout, field-programmable gate arrays synthesis, asymptotic waveform evaluation, asynchronous circuit synthesis using signal t...
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ISBN:
(纸本)0818630108
The conference materials contain 109 papers. design for testability, technology driven IC layout, field-programmable gate arrays synthesis, asymptotic waveform evaluation, asynchronous circuit synthesis using signal transition graphs, clocking of circuits with level sensitive latches, high density module assembly, formal hardware verification, automatic test program generation, testing and diagnosing methods, analog CAD, timing in high-level synthesis, detailed routing, logic synthesis, partitioning and clustering, interconnect analysis, retiming and sensitization conditions, delay testing, asynchronous synthesis, placement and floorplan design, and combinational synthesis are the main topics covered.
The proceedings contains 107 papers from the 1997 ieeeinternationalconference on computer-aideddesign. Topics discussed include: decision diagram applications;optimization and synthesis for reactive systems;estimat...
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The proceedings contains 107 papers from the 1997 ieeeinternationalconference on computer-aideddesign. Topics discussed include: decision diagram applications;optimization and synthesis for reactive systems;estimation of power bounds;interconnect modeling;multi-level synthesis and covering problems;code generation and processor design;high level power prediction and reduction;noise analysis and modeling;timing analysis;microelectromechanical systems;high performance digital circuits;sequential circuit optimization;advanced scheduling techniques;clock design and optimization;circuit simulation and optimization;circuit partitioning;fault simulation and diagnosis;logic synthesis;real time systems;and interconnect optimization.
The proceedings contains 99 papers from the internationalconference on computeraideddesign. Topics discussed include: static scheduling of multi-domain memories for functional verification;verification of shared me...
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The proceedings contains 99 papers from the internationalconference on computeraideddesign. Topics discussed include: static scheduling of multi-domain memories for functional verification;verification of shared memory;predicting the performance of synchronous discrete event simulation systems;system-level exploration and design;analysis of substrate thermal gradient effects on optimal buffer insertion;bus encoding to prevent crosstalk delay;behavioral modeling of analog circuits by wavelet collacation method;simulation-based automatic generation of signomial;and compiler techniques in system level design.
The proceedings contain 133 papers. The topics discussed include: latest advancements to the industry-leading EPDA design flow for silicon photonics;enabling secure in-memory neural network computing by sparse fast gr...
ISBN:
(纸本)9781728123509
The proceedings contain 133 papers. The topics discussed include: latest advancements to the industry-leading EPDA design flow for silicon photonics;enabling secure in-memory neural network computing by sparse fast gradient encryption;clock gating synthesis of netlist with cyclic logic paths;clock gating synthesis of netlist with cyclic logic paths;design technology for scalable and robust photonic integrated circuits;and PABO: pseudo agent-based multi-objective Bayesian hyperparameter optimization for efficient neural accelerator design.
The proceedings contain 164 papers. The topics discussed include: fine-granular computation and data layout reorganization for improving locality;physics-aware differentiable discrete codesign for diffractive optical ...
ISBN:
(纸本)9781450392174
The proceedings contain 164 papers. The topics discussed include: fine-granular computation and data layout reorganization for improving locality;physics-aware differentiable discrete codesign for diffractive optical neural networks;big-little chiplets for in-memory acceleration of DNNs: a scalable heterogeneous architecture;false data injection attacks on sensor systems;stochastic mixed-signal circuit design for in-sensor privacy;sensor security: current progress, research challenges, and future roadmap;design and technology co-optimization utilizing multi-bit flip-flop cells;transitive closure graph-based warpage-aware floorplanning for package designs;SODA synthesizer: an open-source, multi-level, modular, extensible compiler from high-level frameworks to silicon;a scalable methodology for agile chip development with open-source hardware components;a novel semi-analytical approach for fast electromigration stress analysis in multi-segment interconnects;and sub-resolution assist feature generation with reinforcement learning and transfer learning.
The proceedings contain 93 papers. The topics discussed include: physical planning with retiming;corner block list: an effective and efficient topological representation of non-slicing floorplan;modeling non-slicing f...
ISBN:
(纸本)0780364457
The proceedings contain 93 papers. The topics discussed include: physical planning with retiming;corner block list: an effective and efficient topological representation of non-slicing floorplan;modeling non-slicing floorplans with binary trees;event driven simulation without loops or conditionals;observability analysis of embedded software for coverage-directed validation;a methodology for verifying memory access protocols in behavioral synthesis;symbolic debugging scheme for optimized hardware and software;automated data dependency size estimation with a partially fixed execution ordering;effects of global interconnect optimizations on performance estimation of deep submicron design;impact of systematic spatial intra-chip gate length variability on performance of high-speed digital circuits;and miller factor for gate-level coupling delay calculation.
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