The proceedings contain 119 papers. The topics discussed include: verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization;a just-in-time customizable pro...
ISBN:
(纸本)9781479910717
The proceedings contain 119 papers. The topics discussed include: verifying start-up failures in coupled ring oscillators in presence of variability using predictive global optimization;a just-in-time customizable processor;an efficient compiler framework for cache bypassing on GPUs;an efficient graph sparsification approach to scalable harmonic balance (HB) analysis of strongly nonlinear RF circuits;MOMA: mapping of memory-intensive software-pipelined applications for systems with multiple memory controllers;modeling and analysis of (nonstationary) low frequency noise in nano devices: a synergistic approach based on stochastic chemical kinetics;parallel power grid analysis using preconditioned GMRES solver on CPU-GPU platforms;redundancy-aware electromigration checking for mesh power grids;a vectorless framework for power grid electromigration checking;scalable power grid transient analysis via MOR-assisted time-domain simulations.
The proceedings contain 121 papers. The topics discussed include: a scalable decision procedure for fixed-width bit-vectors;generation of optimal obstacle-avoiding rectilinear steiner minimum tree;obstacle-avoiding re...
ISBN:
(纸本)9781605588001
The proceedings contain 121 papers. The topics discussed include: a scalable decision procedure for fixed-width bit-vectors;generation of optimal obstacle-avoiding rectilinear steiner minimum tree;obstacle-avoiding rectilinear steiner tree construction based on steiner point selection;how to consider shorts and guarantee yield rate improvement for redundant wire insertion;power-switch routing for coarse-grain MTCMOS technologies;scheduling with soft constraints;REMiS: run-time energy minimization scheme in a reconfigurable processor with dynamic power-gated instruction set;resilient circuits - enabling energy-efficient performance and reliability;resilience in computer systems and networks;scan power reduction in linear test data compression scheme;compacting test vector sets via strategic use of implications;and pre-ATPG path selection for near optimal post-ATPG process space coverage.
The proceedings contain 127 papers. The topics discussed include: synthesis from multi-cycle atomic actions as a solution to the timing closure problem;on the numbers of variables to represent sparse logic functions;e...
ISBN:
(纸本)9781424428205
The proceedings contain 127 papers. The topics discussed include: synthesis from multi-cycle atomic actions as a solution to the timing closure problem;on the numbers of variables to represent sparse logic functions;effective IR-drop reduction in at-speed scan testing using distribution-controlling X-identification;temperature-aware test scheduling for multiprocessor systems-on-chip;on capture power-aware test data compression for scan-based testing;yield-aware hierarchical optimization of large analog integrated circuits;model reduction via projection onto non-linear manifolds with applications to analog circuits and bio-chemical systems;algorithms for simultaneous consideration of multiple physical synthesis transforms for timing closure;delay-optimal simultaneous technology mapping and placement with applications to timing optimization;and a polynomial time approximation scheme for timing constrained minimum cost layer assignment.
The proceedings contain 145 papers. The topics discussed include: leveraging value locality for efficient design of a hybrid cache in multicore processors;ORCHARD: visual object recognition accelerator based on approx...
ISBN:
(纸本)9781538630938
The proceedings contain 145 papers. The topics discussed include: leveraging value locality for efficient design of a hybrid cache in multicore processors;ORCHARD: visual object recognition accelerator based on approximate in-memory processing;obfuscating the interconnects: low-cost and resilient full-chip layout camouflaging;CycSAT: SAT-based attack on cyclic logic encryptions;threshold-based obfuscated keys with quantifiable security against invasive readout;mixed-cell-height detailed placement considering complex minimum-implant-area constraints;blockage-aware terminal propagation for placement wirelength minimization;ir-drop aware design & technology co-optimization for N5 node with different device and cell height options;an analog sat solver based on a deterministic dynamical system;connecting spectral techniques for graph coloring and Eigen properties of coupled dynamics: a pathway for solving combinatorial optimizations;accelerating functional timing analysis with encoding duplication removal and redundant state propagation;design automation and testing of monolithic 3D ICs: opportunities, challenges, and solutions;leveraging recovery effect to reduce electromigration degradation in power/ground TSV;thermal-sensitive design and power optimization for a 3D Torus-based optical NoC;VoCaM: visualization oriented convolutional neural network acceleration on mobile systems;and offshore oil spill monitoring and detection: improving risk management for offshore petroleum cyber-physical systems.
The conference materials contain 129 papers. The topics covered include sequential fault simulation;testability and reliability in high-level synthesis;binary decision diagrams;interconnect analysis and modeling;new d...
详细信息
ISBN:
(纸本)0818644923
The conference materials contain 129 papers. The topics covered include sequential fault simulation;testability and reliability in high-level synthesis;binary decision diagrams;interconnect analysis and modeling;new developments in IC testing;layout and database aspects in high-level synthesis;synthesis for lookup-based field-programmable gate arrays;efficient simulation techniques;issues in system-level timing;placement algorithms;statistical design and yield analysis;technology mapping for delay and power optimization;layout issues for multichip modules and field-programmable gate arrays;asynchronous circuit synthesis and verification;numerical device simulation;retiming;CAD issues in system design;analog modeling and test;partitioning and floorplanning;sequential logic optimization;Boolean algebraic test generation;scheduling;technology mapping;routing for FPGAs and FPICs;verification and diagnostics;application specific data path synthesis;combinatorial verification;zero-skew clock routing with delay optimization;built-in self-testing;embedded processor design;high performance interconnects;design for testability and diagnosis;buffer and memory sizing;crosstalk reduction;novel design for test techniques;modeling for high-level synthesis;discrete simulation, and topics in physical design.
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