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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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ROS-Lighthouse: An Intrusion Detection System (IDS) in ROS using Ensemble Learning 27

ROS-Lighthouse: An Intrusion Detection System (IDS) in ROS u...

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27th international symposium on Wireless Personal Multimedia Communications, WPMC 2024

作者： Johnson, Stevens Borah, Abinash Paranjothi, Anirudh thomas, Johnson P. Oklahoma State University Department of Computer Science Stillwater United States

ISBN: (纸本)9798350392319

Security concerns of Robot Operating System (ROS) have come to the limelight recently, especially as ROS is paving its way into more applications. ROS lacks built-in security features in its architecture, rendering it susceptible to attacks. Efforts have been made to secure ROS communication;however, the current landscape still poses risks. this study proposes ROSlighthouse, a framework based on machine learning, that probes through the data received by a ROS node to classify intrusions. An Intrusion Detection System (IDS) is created utilizing the Super Learner algorithm to identify intrusions within ROS networks. ROS-lighthouse has been assessed and determined to detect intrusions with accuracies up to 99.907%. Additionally, recommendations and future directions for enhancing ROSlighthouse's connectivity to the internet are provided. © 2024 ieee.

关键词： Lighthouses

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Energy-efficient online resource provisioning for cloud-edge platforms via multi-armed bandits 34

Energy-efficient online resource provisioning for cloud-edge...

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34th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Rey-Jouanchicot, Jordan del Castillo, Juan Angel Lorenzo Zuckerman, Stephane Veronica Belmega, E. CY Cergy Paris Univ CY Tech Cergy France CY Cergy Paris Univ ETIS UMR 8051 ENSEA CNRS F-95000 Cergy France Univ Gustave Eiffel CNRS LIGM F-77454 Marne La Vallee France

ISBN: (数字)9781665451574

ISBN: (纸本)9781665451574

Edge computing is a new paradigm in which data are locally collected, aggregated and preprocessed before being sent to a Cloud platform. Edge devices, typically IoT objects, are characterized by limited computational capabilities, alongside high energy efficiency operations. In smart building or smart city applications, the overall amount of available IoT devices may account for an important computational capacity. Aggregating the idle CPU cycles of several devices would allow performing on-site parallel and distributed computing, while reusing the available resources in the network. Timely and important computational tasks such as video surveillance processing, HPC jobs, or deep neural network training, can be performed with local available resources. this includes local servers or a private, on-site cloud, as opposed to the use of public clouds, thus avoiding security issues and fostering energy efficiency. An ongoing research topic in such a distributed and volatile context is to design novel algorithms for resource provisioning that allow tasks to be distributed over a set of available IoT devices in an efficient manner. this work presents two online, adaptive and robust scheduling techniques, based on the UCB and EXP3 Multi-Armed Bandit algorithms (MABs), for resource management in Cloud-Edge computing based environments while improving performance and reducing energy consumption. the novelty of our adapted algorithms lies in the fact that we explicitly account for unavailable computing IoT devices resulting in a time-varying available set of arms at each stage. Our numerical results show the high relevance of our approach in reaching optimal provisioning policies in time-varying environments.

关键词： Cloud Edge computing resource provisioning online learning multi-armed bandits

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Message from Program Chairs

Proceedings - Symposium on Computer Architecture and High Pe...

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Proceedings - symposium on computer architecture and high performance computing 2024年 X页

作者： Osthoff, Carla Nelson Amaral, J. National Laboratory for Scientific Computing Brazil University of Alberta Canada

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Automatic aggregation of subtask accesses for nested OpenMP-style tasks 34

Automatic aggregation of subtask accesses for nested OpenMP-...

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34th ieee international symposium on computer architecture and high performance computing (SBAC-PAD)

作者： Shaaban, Omar Aguilar, Jimmy Beltran, Vicenc Carpenter, Paul Ayguade, Eduard Labarta Mancho, Jesus Barcelona Supercomp Ctr Barcelona Spain

ISBN: (数字)9781665451550

ISBN: (纸本)9781665451550

Task-based programming is a high performance and productive model to express parallelism. Tasks encapsulate work to be executed across multiple cores or offloaded to GPUs, FPGAs, other accelerators or other nodes. In order to maintain parallelism and afford maximum freedom to the scheduler, the task dependency graph should be created in parallel and well in advance of task execution. A key limitation with OpenMP and OmpSs-2 tasking is that a task cannot be created until all its accesses and its descendents' accesses are known. Current approaches to work around this limitation either stop task creation and execution using a taskwait or they substitute "fake" accesses known as sentinels. this paper proposes the auto clause, which indicates that the task may create subtasks that access unspecified memory regions or it may allocate and return memory at addresses that are of course not yet known. Unlike approaches using taskwaits, there is no interruption to the concurrent creation and execution of tasks, maintaining parallelism and the scheduler's ability to optimize load balance and data locality. Unlike existing approaches using sentinels, all tasks can be given a precise specification of their own data accesses, so that a single mechanism is used to control task ordering, program data transfers on distributed memory and optimize data locality, e.g. on NUMA systems. the auto clause also provides an incremental path to develop programs with nested tasks, by removing the need for every parent task to have a complete specification of the accesses of its descendent tasks. this is redundant information that can be time consuming and error-prone to describe. We present a straightforward runtime implementation that achieves a 1.4 times speedup for n-body with OmpSs-2@Cluster task offloading to 32 nodes and <4% slowdown for three benchmarks with task offloading to 8 nodes. All code is open source.

关键词： HPC Runtime Systems OpenMP OmpSs-2 Task Parallelism Distributed computing

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OpenMDS: An Open-Source Shell Generation Framework for high-performance Design on Multi-Die FPGAs 30

OpenMDS: An Open-Source Shell Generation Framework for High-...

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ieee 30th international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Shin, Gyeongcheol Kim, Junsoo Kim, Joo-Young Korea Adv Inst Sci & Technol Sch Elect Engn Daegeon South Korea

ISBN: (纸本)9781665483322

FPGA is a promising platform in designing a hardware accelerator due to its design flexibility and fast development cycle, despite the device's limited hardware resources. To address this, latest FPGAs have adopted a multi-die architecture providing abundant hardware resources with high yield and cost-benefit. However, the multi-die architecture causes critical timing issues when signal paths cross the die-to-die boundaries, adding another design challenge in using FPGA. We propose OpenMDS, an open-source shell generation framework for high-performance design on multi-die FPGAs. Based on the user's design requirements, it generates an optimized shell for the target FPGA via automated bus pipelining, customized floorplanning, and scalable clocking scheme.

关键词： computer architecture Timing Field programmable gate arrays Open source software Hardware acceleration Pipeline processing

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A NUMA-aware Graph Database for Hybrid Memory System 21

A NUMA-aware Graph Database for Hybrid Memory System

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21st ieee international symposium on Parallel and Distributed Processing with Applications, 13th ieee international Conference on Big Data and Cloud computing, 16th ieee international Conference on Social computing and Networking and 13th international Conference on Sustainable computing and Communications, ISPA/BDCloud/SocialCom/SustainCom 2023

作者： Tan, Shaoheng Liu, Chang Li, Dingding Tang, Yong Zeng, Deze South China Normal University School of Computer Science Guangdong Guangzhou510631 China China University of Geosciences School of Computer Science Hubei Wuhan430074 China

ISBN: (纸本)9798350329223

Compared to traditional relational databases (RDBMS), specialized graph databases (GDBs) can efficiently store and process graph data in both time and space. Hence, domains like social networks often use GDBs for data management, such as representing friendships. Optane DC Persistent Memory Module (DCPMM) is a novel memory device combining byte-addressability, non-volatility, high density and superior performance. Intuitively, applying GDB on DCPMM with the Non-Uniform Memory Access (NUMA) architecture may improve I/O performance, yet the real performance may be unstable due to stacked hardware characteristics. Specifically, DCPMM exhibits serious NUMA effects and unexpected read/write asymmetry compared to DRAM. To tackle these issues, we propose a NUMA-aware graph database called NAPGDB. NAPGDB employs delegated thread pools to improve the latency of accessing remote nodes. Additionally, it categorizes read/write requests into short-running and long-running tasks, with the former being served synchronously instead of using delegated threads to improve CPU utilization. We implement NAPGDB and the experimental results show that NAPGDB can improve the remote throughput by 1.3x-1.7x compared with the multithreaded Redis with RedisGraph. © 2023 ieee.

关键词： Graph Databases

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VIA: A Smart Scratchpad for Vector Units with Application to Sparse Matrix Computations 27

VIA: A Smart Scratchpad for Vector Units with Application to...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Pavon, Julian Valdivieso, Ivan Vargas Barredo, Adrian Marimon, Joan Moreto, Miquel Moll, Francesc Unsal, Osman Valero, Mateo Cristal, Adrian Barcelona Supercomp Ctr Barcelona Spain Univ Politecn Cataluna Barcelona Spain

ISBN: (纸本)9781665422352

Sparse matrix operations are critical kernels in multiple application domains such as high performance computing, artificial intelligence and big data. Vector processing is widely used to improve performance on mathematical kernels with dense matrices. Unfortunately, existing vector architectures do not cope well with sparse matrix computations, achieving much lower performance in comparison with their dense counterparts. To overcome this limitation, we present the Vector Indexed architecture (VIA), a novel hardware vector architecture that accelerates applications with irregular memory access patterns such as sparse matrix computations. there are two main bottlenecks when computing with sparse matrices: irregular memory accesses and index matching. VIA addresses these two bottlenecks with a smart scratchpad that is tightly coupled to the Vector Functional Units within the core. thanks to this structure, VIA improves locality for sparse-dense computations and improves the index matching search process for sparse computations. As a result, VIA achieves significant performance speedup over highly optimized state-of-the-art C++ algebra libraries. On average, VIA outperforms sparse matrix vector multiplication, sparse matrix addition and sparse matrix matrix multiplication kernels by 4.22 x, 6.14x and 6.00 x, respectively, when evaluated over a thousand sparse matrices that arise in real applications. In addition, we prove the generality of VIA by showing that it can accelerate histogram and stencil applications by 4.5x and 3.5x, respectively.

关键词： Sparse Algebra Vector computing Scratchpad Memory

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A Research Retrospective on the AMD Exascale computing Journey 50

A Research Retrospective on the AMD Exascale Computing Journ...

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50th Annual international symposium on computer architecture (ISCA)

作者： Loh, Gabriel H. Aga, Shaizeen Alsop, Johnathan Blagodurov, Sergey Chalmers, Noel Cownie, David Dutu, Alexandru Greathouse, Joseph L. Hossamani, Sachin Kalamatianos, John Lowell, Daniel Manne, Srilatha Mishkin, Michael Potter, Brandon Rao, Karthik Slice, John Vishnu, Abhinav Wyse, Mark Schulte, Michael J. Aguren, Derrick Bauman, Paul T. Boraten, Travis Chen, Shaoming Curtis, Nicholas Eckert, Yasuko Gurumurthi, Sudhanva Huang, Wei Kayiran, Onur Madan, Niti Mashimo, Susumu Nutter, Mark Punniyamurthy, Kishore Rodgers, Gregory Sridharan, Vilas Wasmundt, Samuel Yalavarti, Adithya Ignatowski, Mike Agrawal, Varun Beckmann, Bradford M. Boyer, Michael Cheng, Kevin Del Pino, Joris Erb, Christopher Gutierrez, Anthony Islam, Mahzabeen Kotra, Jagadish Majumdar, Abhinandan McDougall, Damon Paul, Indrani Puthoor, Sooraj Scrbak, Marko van Oostrum, Rene Wilkening, Mark Yudanov, Dmitri Adhinarayanan, Vignesh Aji, Ashwin M. Beigi, Majed Valad Brantley, William C. Chu, Michael L. Duong, Nam Freitag, Chip Hamidouche, Khaled Jayasena, Nuwan Lee, Alan Malaya, Nicholas Mednick, Elliot Poremba, Matthew Raasch, Steven E. Seyedzadeh, Mohammad van Tassell, Eric Wolfe, Noah Adv Micro Devices Inc Santa Clara CA 95054 USA

ISBN: (纸本)9798400700958

the pace of advancement of the top-end supercomputers historically followed an exponential curve similar to (and driven in part by) Moore's Law. Shortly after hitting the petaflop mark, the community started looking ahead to the next milestone: Exascale. However, many obstacles were already looming on the horizon, such as the slowing of Moore's Law, and others like the end of Dennard Scaling had already arrived. Anticipating significant challenges for the overall high-performance computing (HPC) community to achieve the next 1000x improvement, the U.S. Department of Energy (DOE) launched the Exascale computing Program to enable and accelerate fundamental research across the many technologies needed to achieve exascale computing. AMD had the opportunity to contribute to the so-called "*Forward" programs from the DOE, which were a series of public-private partnerships focused on research and co-design activities covering compute architectures, interconnects, memory systems, chiplets and packaging, software stacks, applications, and more. Some of the research from these programs can now be found in the world's first exascale supercomputer, some were a little ahead of their time and may have an impact in the coming years, and others simply did not pan out. In this paper, we provide a retrospective of AMD's nearly decade-long research journey covering how we tried to predict the architecture of a supercomputer a decade into the future, what we got right, what we got wrong, and some of the insights and learnings that we discovered along the way.

关键词： Exascale HPC high-performance computing supercomputing Frontier memory chiplets heterogeneous compute accelerated processing unit research

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Dynamic Resource Allocation and Security Strategies in Cooperative Relaying Systems with Eavesdropping threats 27

Dynamic Resource Allocation and Security Strategies in Coope...

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27th international symposium on Wireless Personal Multimedia Communications, WPMC 2024

作者： Upadhyay, Deepak Sharma, Kunj Bihari Upadhyay, Abhay Gupta, Mridul Venu, Nookala Graphic Era Hill University Dept. of Computer Science and Engineering Dehradun India Graphic Era deemed to be University Dept. of Computer Science and Engineering Dehradun India Graphic Era deemed to be University Dept. of Electronics and Communication Engineering Dehradun India Deemed University Centre for Internet of Things Madhav Institute of Technology and Science Gwalior India

ISBN: (纸本)9798350392319

the dynamic resource allocation and security strategies for cooperative relaying systems proposed here provide significant performance improvements along with robust security features over traditional methods. the method improves throughput, energy efficiency and secrecy capacity by dynamically provisioning resources according to real-time network conditions in conjunction with its interference-suppression techniques such adaptive beamforming and artificial noise. the system is quite good at preventing eavesdropping, and it has such high signal-to-noise ratios that there is a very low error rate. the use case results show that the integrated framework optimizes resource consumption while mitigating security threats, thereby offering a trade-off between existing solutions thus solving some of their shortcomings. Our work demonstrates the opportunity for efficient and secure communication in dynamic environments. © 2024 ieee.

关键词： Energy efficiency

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AI-Enabling Workloads on Large-Scale GPU-Accelerated System: Characterization, Opportunities, and Implications 28

AI-Enabling Workloads on Large-Scale GPU-Accelerated System:...

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28th Annual ieee international symposium on high-performance computer architecture (HPCA)

作者： Li, Baolin Arora, Rohin Samsi, Siddharth Patel, Tirthak Arcand, William Bestor, David Byun, Chansup Roy, Rohan Basu Bergeron, Bill Holodnak, John Houle, Michael Hubbell, Matthew Jones, Michael Kepner, Jeremy Klein, Anna Michaleas, Peter McDonald, Joseph Milechin, Lauren Mullen, Julie Prout, Andrew Price, Benjamin Reuther, Albert Rosa, Antonio Weiss, Matthew Yee, Charles Edelman, Daniel Vanterpool, Allan Cheng, Anson Gadepally, Vijay Tiwari, Devesh Northeastern Univ Boston MA 02115 USA MIT Lincoln Lab Cambridge MA 02139 USA US Air Force Wright Patterson AFB OH 45433 USA

ISBN: (纸本)9781665420273

Production high-performance computing (HPC) systems are adopting and integrating GPUs into their design to accommodate artificial intelligence (AI), machine learning, and data visualization workloads. To aid with the design and operations of new and existing GPU-based large-scale systems, we provide a detailed characterization of system operations, job characteristics, user behavior, and trends on a contemporary GPU-accelerated production HPC system. Our insights indicate that the pre-mature phases in modern AI workflow take up significant GPU hours while underutilizing GPUs, which opens up the opportunity for a multi-tier system. Finally, we provide various potential recommendations and areas for future investment for system architects, operators, and users.

关键词： Systems operation Graphics processing units Data visualization Production Machine learning computer architecture Market research

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