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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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TILT: Achieving higher Fidelity on a Trapped-Ion Linear-Tape Quantum computing architecture 27

TILT: Achieving Higher Fidelity on a Trapped-Ion Linear-Tape...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Wu, Xin-Chuan Debroy, Dripto M. Ding, Yongshan Baker, Jonathan M. Alexeev, Yuri Brown, Kenneth R. Chong, Frederic T. Univ Chicago Dept Comp Sci Chicago IL 60637 USA Duke Univ Dept Phys Durham NC 27706 USA Argonne Natl Lab Computat Sci Div Lemont IL USA Duke Univ Dept Elect & Comp Engn Durham NC USA

ISBN: (纸本)9781665422352

Trapped-ion qubits are a leading technology for practical quantum computing. In this work, we present an architectural analysis of a linear-tape architecture for trapped ions. In order to realize our study, we develop and evaluate mapping and scheduling algorithms for this architecture. In particular, we introduce TILT, a linear "Turing-machine-like" architecture with a multilaser control "head," where a linear chain of ions moves back and forth under the laser head. We find that TILT can substantially reduce communication as compared with comparable-sized Quantum Charge Coupled Device (QCCD) architectures. We also develop two important scheduling heuristics for TILT. the first heuristic reduces the number of swap operations by matching data traveling in opposite directions into an "opposing swap.", and also avoids the maximum swap distance across the width of the head, as maximum swap distances make scheduling multiple swaps in one head position difficult. the second heuristic minimizes ion chain motion by scheduling the tape to the position with the maximal executable operations for every movement. We provide application performance results from our simulation, which suggest that TILT can outperform QCCD in a range of NISQ applications in terms of success rate (up to 4.35x and 1.95x on average). We also discuss using TILT as a building block to extend existing scalable trapped-ion quantum computing proposals.

关键词： Quantum computing Trapped-ion architecture Circuit Optimization

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Banana Crop Health: A Deep Learning-Based Model for Disease Detection and Classification 27

Banana Crop Health: A Deep Learning-Based Model for Disease ...

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27th international symposium on Wireless Personal Multimedia Communications, WPMC 2024

作者： Singh, Shashank Prakash, Pallav Baghel, Gulshan Singh, Anuj Raj, Dharm Agrawal, Amrit Kumar Sharda University Sharda School of Engineering and Technology Department Of Computer Science and Engineering Greater Noida India

ISBN: (纸本)9798350392319

Bananas are a major food crop that feeds billions of people and provides an income to countless others. Nevertheless, they are prone to a range of diseases, which can lead to substantial loss in yield and quality as well as market value. the early diagnosis and accurate monitoring of these pathologies play crucial roles in the planning of disease management and control strategies. In this study, a deep learning-based method is proposed for identification and classification of banana diseases with MobileNetV2 architecture. Dataset: the training dataset used for this model is a large repository of 3012 annotated images, from four different diseases - Panama Disease, Black Sigatoka, Yellow Sigatoka and Bacterial Soft Rot along with the healthy plants. this model was validated on another set of images. the model was relatively high accurate after some small through fine-tuning and advanced image augmentation techniques applied to it. the high-level accuracy in predicting disease in banana shows promise for being a key tool at the early stage to control diseases on plant which helps better management, prevention economic loss and improved agriculture productivity. © 2024 ieee.

关键词： Fruits

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Enabling high-Quality Uncertainty Quantification in a PIM Designed for Bayesian Neural Network 28

Enabling High-Quality Uncertainty Quantification in a PIM De...

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28th Annual ieee international symposium on high-performance computer architecture (HPCA)

作者： Li, Xingchen Wu, Bingzhe Sun, Guangyu Zhang, Zhe Yuan, Zhihang Wang, Runsheng Huang, Ru Niu, Dimin Zheng, Hongzhong Lu, Zhichao Zhao, Liang Chang, Meng-Fan Marvin Guan, Tianchan Si, Xin Peking Univ Beijing Peoples R China Alibaba Grp Inc Hangzhou Peoples R China Hefei Reliance Memory Ltd Hefei Peoples R China Natl Tsing Hua Univ Hsinchu Taiwan Southeast Univ Nanjing Peoples R China Adv Inst Informat Technol Beijing Peoples R China

ISBN: (纸本)9781665420273

Uncertainty quantification measures the prediction uncertainty of a neural network facing out-of-training-distribution samples. Bayesian Neural Networks (BNNs) can provide high-quality uncertainty quantification by introducing specific noise to the weights during inference. To accelerate BNN inference, ReRAM processing-in-memory (PIM) architecture is a competitive solution to provide both high-efficient computing and in-situ noise generation at the same time. However, there normally exists a huge gap between the generated noise in PIM hardware and that required by a BNN model. We demonstrate that the quality of uncertainty quantification is substantially degraded due to this gap. To solve this problem, we propose a holistic framework called W2W-PIM. We first introduce an efficient method to generate noise in ReRAM PIM design according to the demand of a BNN model. In addition, the PIM architecture is carefully modified to enable the noise generation and evaluate uncertainty quality. Moreover, a calibration unit is further introduced to reduce the noise gap caused by imperfection of the noise model. Comprehensive evaluation results demonstrate that W2W-PIM framework can achieve high-quality uncertainty quantification and high energy-efficiency at the same time.

关键词： ReRAM Bayesian Neural Network Analog computing Noise

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ISCA 2023 - Proceedings of the 2023 50th Annual international symposium on computer architecture

ISCA 2023 - Proceedings of the 2023 50th Annual Internationa...

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50th Annual international symposium on computer architecture, ISCA 2023

ISBN: (纸本)9798400700958

the proceedings contain 84 papers. the topics discussed include: Astrea: accurate quantum error-decoding via practical minimum-weight perfect-matching;TaskFusion: an efficient transfer learning architecture with dual delta sparsity for multi-task natural language processing;scaling qubit readout with hardware efficient machine learning architectures;enabling high performance debugging for variational quantum algorithms using compressed sensing;HAAC: a hardware-software co-design to accelerate garbled circuits;inter-layer scheduling space definition and exploration for tiled accelerators;ArchGym: an open-source gymnasium for machine learning assisted architecture design;SHARP: a short-word hierarchical accelerator for robust and practical fully homomorphic encryption;V10: hardware-assisted NPU multi-tenancy for improved resource utilization and fairness;GenDP: a framework of dynamic programming acceleration for genome sequencing analysis;CamJ: enabling system-level energy modeling and architectural exploration for in-sensor visual computing;and an algorithm and architecture co-design for accelerating smart contracts in blockchain.

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Revisiting HyperDimensional Learning for FPGA and Low-Power architectures 27

Revisiting HyperDimensional Learning for FPGA and Low-Power ...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Imani, Mohsen Zou, Zhuowen Bosch, Samuel Rao, Sanjay Anantha Salamat, Sahand Kumar, Venkatesh Kim, Yeseong Rosing, Tajana Univ Calif Irvine Dept Comp Sci Irvine CA 92697 USA Univ Calif San Diego Dept Comp Sci & Engn San Diego CA 92093 USA MIT Dept Elect Engn & Comp Sci Cambridge MA 02139 USA Daegu Gyeongbuk Inst Sci & Technol Informat & Commun Engn Daegu South Korea

ISBN: (纸本)9781665422352

Today's applications are using machine learning algorithms to analyze the data collected from a swarm of devices on the Internet of things (IoT). However, most existing learning algorithms are overcomplex to enable real-time learning on IoT devices with limited resources and computing power. Recently, Hyperdimensional computing (HDC) is introduced as an alternative computing paradigm for enabling efficient and robust learning. HDC emulates the cognitive task by representing the values as patterns of neural activity in high-dimensional space. HDC first encodes all data points to high-dimensional vectors. It then efficiently performs the learning task using a well-defined set of operations. Existing HDC solutions have two main issues that hinder their deployments on low-power embedded devices: (i) the encoding module is costly, dominating 80% of the entire training performance, (ii) the HDC model size and the computation cost grow significantly with the number of classes in online inference. In this paper, we proposed a novel architecture, LookHD, which enables real-time HDC learning on low-power edge devices. LookHD exploits computation reuse to memorize the encoding module and simplify its computation with single memory access. LookHD also address the inference scalability by exploiting HDC governing mathematics that compresses the HDC trained model into a single hypervector. We present how the proposed architecture can be implemented on the existing low power architectures: ARM processor and FPGA design. We evaluate the efficiency of the proposed approach on a wide range of practical classification problems such as activity recognition, face recognition, and speech recognition. Our evaluations show that LookHD can achieve, on average, 28.3 x faster and 97.4 x more energy-efficient training as compared to the state-of-the-art HDC implemented on the FPGA. Similarly, in the inference, LookHD is 2.2 x faster, 4.1 x more energy-efficient, and has 6.3 x smaller model siz

关键词： HyprDimensional computing Brain-inspired computing Machine learning Real-time learning FPGA

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An Experimental Comparison of RISC-V Processors: performance, Power, Area and Security - Special Session Paper 37

An Experimental Comparison of RISC-V Processors: Performance...

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37th ieee international symposium on Defect and Fault Tolerance in VLSI and Nanotechnology Systems, DFT 2024

作者： Lazzeri, Elia Forlin, Bruno Endres Furano, Gianluca Ottavi, Marco Cassano, Luca Politecnico di Milano Dipartimento di Elettronica Informazione e Bioingegneria Italy University of Twente Faculty of Electrical Engineering Mathematics and Computer Science Netherlands Europeran Space Agency European Space Research and Technology Centre Netherlands

ISBN: (纸本)9798350366884

the RISC-V instruction set architecture (ISA) has garnered significant interest from both industry and academia because of its open source nature. Recent years have witnessed a surge in published implementations of the RISC-V ISA, with various companies actively pursuing its adoption in their products. However, a comprehensive analysis comparing these emerging RISC-V processors with each other and against established embedded computing platforms has not yet been published. this paper presents an experimental evaluation of three high-performance RISC-V processors: BOOM, NOEL-V, and CVA6 (formerly Ariane). the investigation is conducted on a Xilinx Kintex-7 Field-Programmable Gate Array (FPGA) platform. We perform a detailed analysis of critical performance metrics, covering area footprint, power consumption, and performance efficiency. Additionally, we assess the security posture of these cores against transient execution attacks, a prominent contemporary security threat. Finally, a comparative evaluation is undertaken between the RISC-V processors and two conventional application-level ARM processors to elucidate technological discrepancies and application suitability. this analysis aims to provide valuable insights into the current state and potential of RISC-V processors within the embedded computing domain. © 2024 ieee.

关键词： ARM processors

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ETTE: Efficient Tensor-Train-based computing Engine for Deep Neural Networks 23

ETTE: Efficient Tensor-Train-based Computing Engine for Deep...

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50th Annual international symposium on computer architecture (ISCA)

作者： Gong, Yu Yin, Miao Huang, Lingyi Xiao, Jinqi Sui, Yang Deng, Chunhua Yuan, Bo Rutgers State Univ New Brunswick NJ 08901 USA ScaleFlux Inc Milpitas CA USA

ISBN: (纸本)9798400700958

Tensor-train (TT) decomposition enables ultra-high compression ratio, making the deep neural network (DNN) accelerators based on this method very attractive. TIE, the state-of-the-art TT based DNN accelerator, achieved high performance by leveraging a compact inference scheme to remove unnecessary computations and memory access. However, TIE increases memory costs for stage-wise intermediate results and additional intra-layer data transfer, leading to limited speedups even the models are highly compressed. To unleash the full potential of TT decomposition, this paper proposes ETTE, an algorithm and hardware co-optimization framework for Efficient Tensor-Train Engine. At the algorithm level, ETTE proposes new tensor core construction and computation ordering mechanism to reduce stage-wise computation and storage cost at the same time. At the hardware level, ETTE proposes a lookahead-style across-stage processing scheme to eliminate the unnecessary stage-wise data movement. By fully leveraging the decoupled input and output dimension factors, ETTE develops an efficient low-cost memory partition-free access scheme to efficiently support the desired matrix transformation. We demonstrate the effectiveness of ETTE via implementing a 16PE hardware prototype with CMOS 28nm technology. Compared with GPU on various workloads, ETTE achieves 6.5x - 253.1x higher throughput and 189.2x - 9750.5x higher energy efficiency. Compared with the state-of-the-art DNN accelerators, ETTE brings 1.1x - 58.3x, 2.6x - 1170.4x and 1.8x - 2098.2x improvement on throughput, energy efficiency and area efficiency, respectively.

关键词： tensor decomposition neural networks low rank accelerator

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A high-performance Hardware architecture for ECC Point Multiplication over Curve25519 30

A High-Performance Hardware Architecture for ECC Point Multi...

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ieee 30th international symposium on Field-Programmable Custom computing Machines (FCCM)

作者： Wu, Guiming He, Qianwen Jiang, Jiali Zhang, Zhenxiang Long, Xin Zhao, Yuan Zou, Yinchao Alibaba Grp Hangzhou Peoples R China Ant Grp Hangzhou Peoples R China

ISBN: (纸本)9781665483322

As one of the most secure ECC curves, Curve25519 is employed by some secure protocols, such as TLS 1.3, IRTF's RFC7748, Diffie-Hellman Private Set Intersection (DH-PSI) protocol, etc. high performance implementation of ECC is required, especially for the DH-PSI protocol. Point multiplication, the chief cryptographic primitive in ECC, is computationally expensive. To improve the performance of DH-PSI protocol, we propose a novel and high-performance hardware architecture for point multiplication over Curve25519. the proposed architecture features a pipelined Finite-field Arithmetic Unit (FAU) and a simple and highly efficient instruction set architecture (ISA). Compared to the best existing work on Xilinx Zynq 7000 series FPGA, our implementation with one Processing Element (PE) can achieve 3.14x speedup on the same device. To the best of our knowledge, our implementation appears to be the fastest among the state-of-the-art works. We also have implemented our proposed architecture consisting of 4 Compute Groups (CGs), each with 16 PEs, on an Intel Agilex AGF027 FPGA. the experimental results show the peak performance of 4.52 Mops/s (million point multiplication operations per seconds) can be achieved. Moreover, the measured performance of 4.48 Mops/s is achieved, with the PE utilization of 99% and at the cost of 86 Watts power, which is the record-setting performance for point multiplication over Curve25519 on FPGAs.

关键词： performance evaluation Protocols Power measurement Costs Instruction sets computer architecture Elliptic curve cryptography

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FACT: FFN-Attention Co-optimized Transformer architecture with Eager Correlation Prediction 23

FACT: FFN-Attention Co-optimized Transformer Architecture wi...

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50th Annual international symposium on computer architecture (ISCA)

作者： Qin, Yubin Wang, Yang Deng, Dazheng Zhao, Zhiren Yang, Xiaolong Liu, Leibo Wei, Shaojun Hu, Yang Yin, Shouyi Tsinghua Univ Beijing Peoples R China

ISBN: (纸本)9798400700958

Transformer model is becoming prevalent in various AI applications with its outstanding performance. However, the high cost of computation and memory footprint make its inference inefficient. We discover that among the three main computation modules in a Transformer model (QKV generation, attention computation, FFN), it is the QKV generation and FFN that contribute to the most power cost. While the attention computation, focused by most previous works, only has decent power share when dealing with extremely long inputs. therefore, in this paper, we propose FACT, an efficient algorithm-hardware co-design optimizing all three modules of Transformer. We first propose an eager prediction algorithm which predicts the attention matrix before QKV generation. It further detects the unnecessary computation in QKV generation and assigns mixed-precision FFN with the predicted attention, which helps improve the throughput. Further, we propose FACT accelerator to efficiently support eager prediction with three designs. It avoids the large overhead of prediction by using log-based add-only operations for prediction. It eliminates the latency of prediction through an out-of-order scheduler that makes the eager prediction and computation work in full pipeline. It additionally avoids memory access conflict in the mixed-precision FFN with a novel diagonal storage pattern. Experiments on 22 benchmarks show that our FACT improves the throughput of the whole Transformer by 3.59x on the geomean average. It achieves an enviable 47.64x and 278.1x energy saving when computing attention, compared to previous attention-optimization-only SOTA works ELSA and Sanger. Further, FACT achieves an energy efficiency of 4388 GOPS/W performing the whole Transformer layer on average, which is 94.98x higher than Nvidia V100 GPU.

关键词： transformer hardware accelerator efficient computing algorithm-hardware co-design neural network

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Tensor Casting: Co-Designing Algorithm-architecture for Personalized Recommendation Training 27

Tensor Casting: Co-Designing Algorithm-Architecture for Pers...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Kwon, Youngeun Lee, Yunjae Rhu, Minsoo Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon South Korea

ISBN: (纸本)9781665422352

Personalized recommendations are one of the most widely deployed machine learning (ML) workload serviced from cloud datacenters. As such, architectural solutions for high-performance recommendation inference have recently been the target of several prior literatures. Unfortunately, little have been explored and understood regarding the training side of this emerging ML workload. In this paper, we first perform a detailed workload characterization study on training recommendations, root-causing sparse embedding layer training as one of the most significant performance bottlenecks. We then propose our algorithm-architecture co-design called Tensor Casting, which enables the development of a generic accelerator architecture for tensor gather-scatter that encompasses all the key primitives of training embedding layers. When prototyped on a real CPU-GPU system, Tensor Casting provides 1.9-21 x improvements in training throughput compared to state-of-the-art approaches.

关键词： computer architecture memory-centric machine learning deep learning recommendation system

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