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检索条件"任意字段=IEEE 27th International Symposium on Computer Architecture and High Performance Computing"

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Integrated Modeling of Wireless System performance under Beaulieu-Xie Fading and κ-μ Co-Channel Interference: A Multi-Dimensional Exploration 27

Integrated Modeling of Wireless System Performance under Bea...

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27th international symposium on Wireless Personal Multimedia Communications, WPMC 2024

作者： Upadhyay, Deepak Sharma, Kunj Bihari Sharma, Rashmi Venu, Nookala Graphic Era Hill University Dept. of Computer Science and Engineering Dehradun India Graphic Era deemed to be University Dept. of Computer Science and Engineering Dehradun India Department of CSE Pune India Madhav Institute of Technology and Science Deemed University Centre for Internet of Things Gwalior India

ISBN: (纸本)9798350392319

this paper proposes simulation and analysis to discuss how the fading affects the wireless signal waves on different fading levels. Four types of fading: (i) no fading, (ii) a low level of fading, (iii) moderate level of fading and (iv), high level of fading was considered for simulating the signal amplitude over time. Selected fading levels were 'added' to model real world wireless scenarios in which both environmental and interference conditions are at play. the results indicated that in the absence of fading, the amplitude of the signal wave was continuous and not changed significantly;however, from low to severe fading, there could be directly proportional soaring fluctuations in its proper amplitude corresponding to lose of signal strength. Together, these findings underscore the importance of adaptive signal processing techniques and robust modulation strategies in suppressing the degradative effects of fading against the desirable characteristics of proper signal integrity and reliable performance. the findings highlight one reality in communications: understanding fading is critical for designing ultrareliable wireless systems that perform consistently across a variety of operational settings. the knowledge extracted based on this study would further add to novel way of designing robust strategies for Signal resilience and Communication reliability emerged in future wireless networks. © 2024 ieee.

关键词： Cochannel interference

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A Beacon Rate Adjustment Scheme based on Autonomic computing for 5G-V2X 27

A Beacon Rate Adjustment Scheme based on Autonomic Computing...

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27th international Workshop on computer Aided Modeling and Design of Communication Links and Networks (CAMAD)

作者： Hafi, Houda Abdou, Wahabou Abdelhamid Mehri Univ Constantine Algeria Univ Burgundy LIB Lab Dijon France

ISBN: (数字)9781665461290

ISBN: (纸本)9781665461290

Transport services issues are one of the motivating reasons that push research and engineering communities to design and build smart cities. the fifth generation of mobile communications (5G) and Intelligent Transportation Systems (ITS) play a major role to improve transportation efficiency. Two kinds of messages are basically transmitted in 5G-enabled ITS - event-driven and periodic messages. the former are sent whenever a road hazard event like traffic accidents is detected, whereas the latter are generated by each vehicle to advise neighbors about its status information like position, speed, and direction. A high transmission rate of periodic messages consumes a large amount of bandwidth and causes a channel congestion, as well as, a low transmission rate could alter the neighbors discovery process. In this work, a simple and efficient self-adaptive beacons transmission scheme based on autonomic computing is proposed. the purpose is to reduce the overhead in the network and give more chance to higher priority traffic (like immediate emergency message) to access to the radio channel without distorting the view of node's local topology. the solution is validated with a safety message broadcasting protocol. the simulation results show that the proposed mechanism improves the protocol's performance.

关键词： 5G C-V2X beacon rate autonomic computing congestion avoidance

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AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-Tolerant Quantum computers 28

AFS: Accurate, Fast, and Scalable Error-Decoding for Fault-T...

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28th Annual ieee international symposium on high-performance computer architecture (HPCA)

作者： Das, Poulami Pattison, Christopher A. Manne, Srilatha Carmean, Douglas M. Svore, Krysta M. Qureshi, Moinuddin Delfosse, Nicolas Georgia Inst Technol Atlanta GA 30332 USA CALTECH Pasadena CA 91125 USA Microsoft Quantum Redmond WA USA Microsoft Res Redmond WA USA

ISBN: (纸本)9781665420273

Quantum computers promise computational advantages for many important problems across various application domains. Unfortunately, physical quantum devices are highly susceptible to errors that limit us from running most of these quantum applications. Quantum Error Correction (QEC) codes are required to implement Fault-Tolerant Quantum computers (FTQC) on which computations can be performed without encountering errors. Error decoding is a critical component of quantum error correction and is responsible for transforming a set of qubit measurements generated by the QEC code, called the syndrome, into error locations and error types. For the feasibility of implementation, error decoders must not only identify errors with high accuracy, but also be fast and scalable to a large number of qubits. Unfortunately, most of the prior works on error decoding have focused primarily only on the accuracy and have relied on software implementations that are too slow to be of practical use. Furthermore, these studies only look at designing a single decoder and do not analyze the challenges involved in scaling the storage and bandwidth requirements when performing error correction in large systems with thousands of qubits. In this paper, we present AFS, an accurate, fast, and scalable decoder architecture that is designed to operate in the context of systems with hundreds of logical qubits. We present the hardware implementation of AFS, which is based on the Union Find decoding algorithm and employs a three-stage pipelined design. AFS provides orders of magnitude higher accuracy compared to recent SFQ-based hardware decoders (logical error rate of 6 x 10(-10) for physical error rate of 10(-3)) and low decoding latency (42ns on average), while being robust to measurement errors introduced while extracting syndromes during the QEC cycles. We also reduce the amount of decoding hardware required to perform QEC simultaneously on all the logical qubits by co-designing the micro-architectur

关键词： Quantum computing Quantum error correction Fault-tolerant quantum computing Decoding Union-Find decoding Surface codes

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DCT Implementation on a Custom FPGA RISC-V Processor 65

DCT Implementation on a Custom FPGA RISC-V Processor

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65th international symposium ELMAR, ELMAR 2023

作者： Harmina, Tomislav Hofman, Daniel Benjak, Jakov University of Zagreb Faculty of Electrical Engineering and Computing Zagreb Croatia

ISBN: (纸本)9798350325126

this paper presents our implementation of an Out-of-Order RISC-V core design. the increasing relevance of open-standard computer architectures and corresponding tools makes the development of custom hardware an increasingly attractive alternative to off-the-shelf components. RISC-V is such an open Instruction Set architecture (ISA) that has become widely used in recent years, especially in low-cost microcontrollers, but also in high-performance computing in recent years. Here we showcase a custom-developed core capable of executing the Discrete Cosine Transform algorithm which gives the core potential uses in image and video processing. Problems with developing such a core are presented and future possibilities and improvements are discussed. © 2023 ieee.

关键词： computer architecture

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LazyBatching: An SLA-aware Batching System for Cloud Machine Learning Inference 27

LazyBatching: An SLA-aware Batching System for Cloud Machine...

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27th ieee international symposium on high-performance computer architecture (HPCA)

作者： Choi, Yujeong Kim, Yunseong Rhu, Minsoo Korea Adv Inst Sci & Technol Sch Elect Engn Daejeon South Korea

ISBN: (纸本)9781665422352

In cloud ML inference systems, batching is an essential technique to increase throughput which helps optimize total-cost-of-ownership. Prior graph batching combines the individual DNN graphs into a single one, allowing multiple inputs to be concurrently executed in parallel. We observe that the coarse-grained graph batching becomes suboptimal in effectively handling the dynamic inference request traffic, leaving significant performance left on the table. this paper proposes LazyBatching, an SLA-aware batching system that considers both scheduling and batching in the granularity of individual graph nodes, rather than the entire graph for flexible batching. We show that LazyBatching can intelligently determine the set of nodes that can be efficiently batched together, achieving an average 15x, 1.5x, and 5.5x improvement than graph batching in terms of average response time, throughput, and SLA satisfaction, respectively.

关键词： computer architecture machine learning deep learning inference server batching

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Cao Robot for Taiwanese/English Knowledge Graph Application 27

Cao Robot for Taiwanese/English Knowledge Graph Application

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27th Conference on the Oriental COCOSDA international Committee for the Co-Ordination and Standardisation of Speech Databases and Assessment Techniques, O-COCOSDA 2024

作者： Lee, Chang-Shing Wang, Mei-Hui Tseng, Guan-Ying Yue, Chao-Cyuan Hsieh, Hao-Chun Reformat, Marek National University of Tainan Dept. of Computer Science and Information Engineering Tainan Taiwan University of Alberta Dept. of Electrical and Computer Engineering EdmontonAB Canada

ISBN: (纸本)9798331506032

this paper proposes a Content Attention Ontology (CAO) robot for constructing Taiwanese/English Knowledge Graphs (KGs) by prompting audio or texts to Large Language Models (LLMs), including TAIDE, Zephyr, and Llama 3.1. the collected data includes lecture videos from the ieee WCCI 2024 in Japan and the 2024 National Language Development Forum in Taiwan, along with students' learning data from the 2024 Summer School on Taiwanese/English Human and Robot Co-Learning at Rende Elementary School (RDES). In addition, the fundamental concepts of Computational Intelligence (CI) and Quantum CI (QCI) learning were incorporated into the study. the generative KGs highlight important concepts, relations, and communities within the collected teaching and learning data. Additionally, we utilized data from subjects wearing braincomputer interface (BCI) devices while speaking Taiwanese/English to generate KGs. We also compared the differences in these KGs and analyzed the similarities between the transcribed texts of lectures and learners. In the future, we plan to expand the CAO robot to more validation fields across Taiwan, aiming to engage young students in speaking Taiwanese while concurrently enhancing their English language skills through interaction with the robot. © 2024 ieee.

关键词： Knowledge graph

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Cascading Structured Pruning: Enabling high Data Reuse for Sparse DNN Accelerators 22

Cascading Structured Pruning: Enabling High Data Reuse for S...

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49th ieee/ACM Annual international symposium on computer architecture (ISCA)

作者： Hanson, Edward Li, Shiyu Li, Hai 'Helen' Chen, Yiran Duke Univ Durham NC 27706 USA

ISBN: (纸本)9781450386104

performance and efficiency of running modern Deep Neural Networks (DNNs) are heavily bounded by data movement. To mitigate the data movement bottlenecks, recent DNN inference accelerator designs widely adopt aggressive compression techniques and sparse-skipping mechanisms. these mechanisms avoid transferring or computing with zero-valued weights or activations to save time and energy. However, such sparse-skipping logic involves large input buffers and irregular data access patterns, thus precluding many energy-efficient data reuse opportunities and dataflows. In this work, we propose Cascading Structured Pruning (CSP), a technique that preserves significantly more data reuse opportunities for higher energy efficiency while maintaining comparable performance relative to recent sparse architectures such as SparTen. CSP includes the following two components: At algorithm level, CSP-A induces a predictable sparsity pattern that allows for low-overhead compression of weight data and sequential access to both activation and weight data. At architecture level, CSP-H leverages CSP-A's induced sparsity pattern with a novel dataflow to access unique activation data only once, thus removing the demand for large input buffers. Each CSP-H processing element (PE) employs a novel accumulation buffer design and a counter-based sparse-skipping mechanism to support the dataflow with minimum controller overhead. We verify our approach on several representative models. Our simulated results show that CSP achieves on average 15x energy efficiency improvement over SparTen with comparable or superior speedup under most evaluations.

关键词： MLAcceleration Model Compression Hardware/software co-design Low Power Microarchitecture

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Design of a Smart Metering Device with Edge computing for Monitoring Silicon Photovoltaic Panels 27

Design of a Smart Metering Device with Edge Computing for Mo...

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27th international Workshop on computer Aided Modeling and Design of Communication Links and Networks (CAMAD)

作者： Garcia-Valle, Gonzalo Colodrero, Silvia Cuadrat, Victor Gutierrez, Guillermo Beneitez, Sirio Martinez-Navas, Sergio Leitat Adv Engn Terrassa Spain Leitat Energy Convers & Photon Terrassa Spain

ISBN: (数字)9781665461290

ISBN: (纸本)9781665461290

Optimizing power generation with photovoltaic panels seeks to achieve the best performance and efficiency, both of single panels and grids comprising several of them. the outcomes depend on ambient conditions, such as irradiance or temperature, but also on external causes (e.g., soiling) that may lead to critical power losses. this paper proposes a smart metering device containing sensors to monitor these panels continuously by collecting I-V curves, a Maximum Power Point Tracker (MPPT) to maintain the optimal operation, as well as security elements to prevent external accesses and protect the generated data. the objective is to create a predictive maintenance system with artificial intelligence algorithms on the edge. Developing those algorithms requires a characterization of the selected panels to get optimal results, detecting failures and troubles swiftly, both of the panel and the smart device. Moreover, periodically or in case of noteworthy events, the device reports the information to a cloud platform by using LoRa 2.4GHz communication protocol. the device must ensure the proper operation of panels, allowing to take sustainable corrective measures by preventing an unnecessary waste of resources (electricity or water, among others). the aim is to avoid irreparable failures that imply high costs and reach high efficiency of the monitoring system and the energy generation process.

关键词： PV panels predictive maintenance IoT edge computing

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DigiQ: A Scalable Digital Controller for Quantum computers Using SFQ Logic 28

DigiQ: A Scalable Digital Controller for Quantum Computers U...

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28th Annual ieee international symposium on high-performance computer architecture (HPCA)

作者： Jokar, Mohammad Reza Rines, Richard Pasandi, Ghasem Cong, Haolin Holmes, Adam Shi, Yunong Pedram, Massoud Chong, Frederic T. Univ Chicago Dept Comp Sci Chicago IL 60637 USA Univ Southern Calif Dept Elect & Comp Engn Los Angeles CA 90007 USA Super Tech Chicago IL USA NVIDIA Santa Clara CA USA Amazon Braket Seattle WA USA HRL Labs LLC Malibu CA USA

ISBN: (纸本)9781665420273

the control of cryogenic qubits in today's superconducting quantum computer prototypes presents significant scalability challenges due to the massive costs of generating/routing the analog control signals that need to be sent from a classical controller at room temperature to the quantum chip inside the dilution refrigerator. thus, researchers in industry and academia have focused on designing in-fridge classical controllers in order to mitigate these challenges. Due to the maturity of CMOS logic, many industrial efforts (Microsoft, Intel) have focused on Cryo-CMOS as a near-term solution to design in-fridge classical controllers. Meanwhile, Superconducting Single Flux Quantum (SFQ) is an alternative, less mature classical logic family proposed for large-scale in-fridge controllers. SFQ logic has the potential to maximize scalability thanks to its ultra-high speed and very low power consumption. However, architecture design for SFQ logic poses challenges due to its unconventional pulse-driven nature and lack of dense memory and logic. thus, research at the architecture level is essential to guide architects to design SFQ-based classical controllers for large-scale quantum machines. In this paper, we present DigiQ, the first system-level design of a Noisy Intermediate Scale Quantum (NISQ)-friendly SFQ-based classical controller. We perform a design space exploration of SFQ-based controllers and co-design the quantum gate decompositions and SFQ-based implementation of those decompositions to find an optimal SFQ-friendly design point that trades area and power for latency and control while ensuring good quantum algorithmic performance. Our co-design results in a single instruction, multiple data (SIMD) controller architecture, which has high scalability, but imposes new challenges on the calibration of control pulses. We present software-level solutions to address these challenges, which if unaddressed would degrade quantum circuit fidelity given the imperfections of q

关键词： SFQ-based quantum gate Quantum optimal control Scalable quantum computer Cryogenic electronic

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performance and Error Tolerance of Stochastic computing-Based Digital Filter Design

Performance and Error Tolerance of Stochastic Computing-Base...

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ieee Design and Diagnostics of Electronic Circuits and Systems (DDECS)

作者： Roshwin Sengupta Ilia Polian John P. Hayes Institute of Computer Architecture and Computer Engineering University of Stuttgart Stuttgart Germany Computer Engineering Laboratory University of Michigan Ann Arbor Michigan USA

Recent advances in near-sensor computing have prompted the need to design low-cost digital filters for edge devices. Stochastic computing (SC), leveraging its probabilistic bit-streams, has emerged as a compelling alternative to traditional deterministic computing for filter design. this paper examines error tolerance, area and power efficiency, and accuracy loss in SC-based digital filters. Specifically, we investigate the impact of various stochastic number generators and increased filter complexity on both FIR and IIR filters. Our results indicate that in an error-free environment, SC exhibits a 49% area advantage and a 64% power efficiency improvement, albeit with a slight loss of accuracy, compared to traditional binary implementations. Furthermore, when the input bit-streams are subject to a 2% bit-flip error rate, SC FIR and SC IIR filters have a much smaller performance degradation (1.3X and 1.9X, respectively) than comparable binary filters. In summary, this work provides useful insights into the advantages of stochastic computing in digital filter design, showcasing its robust error resilience, significant area and power efficiency gains, and trade-offs in accuracy compared to traditional binary approaches.

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